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1、苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿外文文献资料苏州大学 应用技术学院 11电子 1116405049张毛毛Single-stage single-switch power factor correction AC/DC converter A single-stage single-switch power factor correction AC/DC converter is proposed in which the power factor correction (PFC) induction is connect to a tap on the primar
2、y winding of the DC/DC fly back converter stage; there is direct energy transfer of a part of the input energy tot he output and the DC-bus voltage feedback. The additional discharge path in the PFC induction and DC-bus voltage feedback effectively suppresses the DC-bus voltage and increases the ove
3、r all efficiency. Experimental results for a 60W converter at a constant switching frequency of 70 kHz are obtained to show the performance of the proposed converter. It is shown that the voltage across the DC-bus capacitor can be held below 405V even though the converter operates in a wide range of
4、 input voltages (90V-265VAC) and the measured input current harmonics satisfy the IEC。1 Introduction Many PFC AC/DC converters have been presented in recent years. PFC techniques can be divided into two categories: a single-stage approach and a two-stage approach. The two-stage approach is the most
5、commonly used approach. Conventional two-stage PFC converters involve the use of cascading two power-processing stages,responsible for power factor correction and output volt age. A PFC converter is adopted at the front-end to force the line current tracking the line voltage and another conventional
6、 DC/DC converter is cascaded after the PFC stage to obtain the desired tightly regulated output voltage.This approach can obtain very good performance, such as high power factor, and low voltage stress. However, due to the use of two power-processing stages, conversion efficiency is reduced and an a
7、dditional PFC stage adds components and complexity. Consequently the overall cos tin creases. The two-stage approach has disadvantages of low power density, control complexity, and high cost.To reduce the overall size and cost, a number of s i g lest age PFC converters have been developed in the lit
8、erature witches so that the PFC switch and its controller can be eliminated. The single-stage approach is specially attractive in low-cost and low-power applications due to its simple power stage and control circuit. However,it still has several drawbacks such as high current stress in power switch
9、and high DC-bus voltage stress. Its major drawback is a high voltage stress on the DC-bus capacitor.Many single-stage PFC AC/DC converters suffer from high DC-bus voltage stress at light load and high line, which makes these converters impractical. A high DC-bus voltage means high component rating,
10、high cost and low voltage stress. Experimental results for a 60W converter a ta constant switching frequency of 70 kHz are obtained to show the performance of the proposed converter. It is how n that the voltage across the DC-bus capacitor can beheld below 404V even though the converter operates in
11、a wide range of input voltages (90V-265VAC) and the measured input current harmonics satisfy the IEC 61000-3-2Class D requirements.2 Analysis of proposed converter Figure 1 shows the equivalent circuits of the proposed converter. The secondary winding Nb is added in the PFC boost induction. The firs
12、t transformer T1 in DC/DC part can be operated either in CCM or DCM depending on the load conditions as in the conventional fly back converter. For simplification, DC/DC part is assumed to operate in CCM for entire line period. The second transformer T2 is operated in DCM. According to the operation
13、 of T2, When the DC-bus voltage feedback value V1(=np2Vab, np2=N2/Np) is higher than the rectified line input voltage vi, the converter operation enters region A. In region A only T1 is operating and Db is reverse-biased during the on-time period S. When Vi is higher than V1 and lower than V2 the op
14、eration converter enters region B. In this region T1 and T2 work like fly back transformers; V2 is determined by V d+(n1-n a)V o where n1=N1/N s and n a=Na/Nb.When vi is higher than V2 the converter operation enters region C. In this region T1 works like a fly back transformer and T2 works like a bo
15、ost induction. Since the voltage vi is V m sin o t in the first quarter of line period, the boundary times t x and t y for three modes are given byFig. 1 Equivalent circuit2.1 Region A operation In region A the input voltage vi is lower than the DC-bus voltage feedback value V l=(N2/Np)V d. Only the
16、 DC/DC part operates. It delivers power from the DC-bus capacitor Cd to the load RL through T1. At to the switch S is turned on. Since the DC-bus voltage V d is applied across the mag net i sing inductance Lm1, the mag n e ti sing current iLm1 increases linearly from its low peak value I m A,L as fo
17、llows:At t1 the switch S is turned off and the output diode D1 is on. Since -n p V o is applied across the mag n e ti sing inductance Lm1, the current decreases linearly from its high peak value I m A,H as follows:The diode current iD1 is given byFrom (3) and (4) the voltage gain is determined as fo
18、llows:Since the DC/DC part operates in CCM, the duty cycle D does not change with the load variation. From (6) the turn ration n p can be determined byThe duty cycle D can be obtained asThe duty cycle D is also effective in regions B and C. The power P1 delivered by the transformer T1 is determined
19、asSince the power P1 delivered by the transformer T1 should be equal to the output power Po (=Vo2 /RL), the following relation is obtained:Consequently the DC-bus capacitor provides the whole power to the load. From (3), (6) and (10), the high and low peak values of iLm1 are determined by2.2 Region
20、B operationWhen the voltage vi is higher than V1 and lower than V2, the converter operates in region B. PFC cell operates as DCM fly back converter. At t0 the switch S is turned on. Since the DC-bus voltage V d is applied across the mag n e ti sing inductance Lm1, the mag n e ti sing current iLm1 in
21、creases linearly from its low peak value I m B,L as follows:The mag n e ti sing current iLm2 increases linearly from zero as follows:Sincethe DC-bus capacitor current i Cd, the current i2, and the switch current is are given by From (15) it can be seen that the mag n e ti sing current iLm1 is suppli
22、ed by the mag n e ti sing current iLm2 and the discharging current i Cd of the DC-bus capacitor Cd. From (17) the switch current is is also composed of the two components. The conduction loss can be reduced by selecting smaller np1. At t1 the switch S is turned off and the output diodes D1 and D2 ar
23、e on. Since n p V o is applied across the mag n e ti sing inductance Lm1, the current iLm1decreases linearly from its high peak value I m B,H as follows:Since the diode D2 is on, _n a V o is applied across the mag n e ti sing inductance Lm2 and the current iLm2 decreases linearly from its peak value
24、 I m,p as follows: The peak value I m,p is given byFrom (20)At t2 the current iLm2 arrives at zero and the diode D2 is turned off. The power P1 delivered by the transformer T1 is given byThe power P2 delivered by the transformer T2 is determined bySince the sum of the power P1 delivered by the trans
25、former T1 and the power P2 delivered by the transformer T2 should be equal to the output power Po, the following relation isobtained:From (6), (13) and (24), the high and low peak values of iLm1 are determined by2.3 Region C operationWhen the voltage vi is higher than V2 the converter operates in re
26、gion C. The PFC cell operates as a DCM boost converter and the diode D2 is off in this region. At t0 the switch S is turned on, iLm1 increases linearly asfollows:iLm2 increases linearly as in region B. Equations (9)(11) are also effective in this region. The mag n e ti sing current iLm1 is supplied
27、by the mag n e ti sing current iLm2 and the dischargingcurrent i Cd of the DC-bus capacitor Cd. When the current iLm2 is high enough that np2iLm2 exceeds iLm1, the DC-bus capacitor can be in charging mode during the on time interval of S. This charging mode may occur near the line peak voltage as fo
28、llows:At t1 the switch S is turned off and the output diodes D1.Since _n p V o is applied across the mag n e ti sing inductance Lm1, the current iLm1 decreases linearly from its high peak value I m C,H as follows:Since the diode Db is on, the voltage across the mag n e ti sing inductance Lm2 is _V d
29、_n1Vo+vi and the current iLm2 decreases linearly from its peak value I m,p as follows:The peak value I m,p is given byFrom (31)Sincethe current i1, the DC-bus capacitor current i Cd, and the diode current iD1 are determine as follows:The current iD1 is composed of two components which are from Lm1 a
30、nd Lm2. Therefore, there is direct power transfer from the line input to the load during the switch off-time. As a result the overall efficiency can be improved. At t2, the current iLm2 arrives at zero and the diode Db is turned off. The current iD1 is npiLm1. Since the output power should be equal
31、to the sum of the power from Lm1 and the power from Lm2, the following relation isobtained:From (6), (13) and (24), the high and low peak values of iLm1 are determined byTitle: AC/DC converter circuitAbstract: There is disclosed an AC/DC converter circuit. The circuit comprises: an input terminal fo
32、r receiving an AC supply voltage; a driver circuit adapted to supply a DC drive current or voltage to an output of the circuit based on a signal provided to a control terminal of the driver circuit; and an AC coupling network connected between the input terminal and the control terminal of the drive
33、r circuit. The AC coupling network is adapted to derive a signal from an AC supply voltage received by the input terminal and to supply the derived signal to the control terminal of the driver circuit. 1. An AC/DC converter circuit comprising: an input terminal for receiving an AC supply voltage; a
34、driver circuit adapted to supply a DC drive current or voltage to an output of the circuit based on a signal provided to a control terminal of the driver circuit; and an AC coupling network connected between the input terminal and the control terminal of the driver circuit, wherein the AC coupling n
35、etwork is adapted to derive a signal from an AC supply voltage received by the input terminal and to supply the derived signal to the control terminal of the driver circuit. 2. The circuit of claim 1, wherein the AC coupling network is adapted to derive a signal based on the phase of the AC supply v
36、oltage received by the input terminal. 3. The circuit of claim 1 or 2, wherein the driver circuit is an integrated circuit. 4. The circuit of claim 3, wherein the integrated circuit is an AC/DC converter driver. 5. The circuit of any preceding claim, further comprising a rectifier adapted to rectify
37、 an AC supply voltage received by the input terminal. 6. The circuit of any preceding claim, wherein the AC coupling network comprises a capacitor and resistor connected in series. 7. The circuit of any preceding claim, wherein the control terminal of the driver circuit is adapted to control at leas
38、t one parameter of the driver circuit. 8. The circuit of claim 1, wherein the at least one parameter comprises at least one of: a peak induction current; a switching frequency of the driver circuit; and a pulse interval. 9. The circuit of any preceding claim, further comprising a DC coupling arrange
39、ment, and wherein the driver circuit is further adapted to supply the DC drive current or voltage to the output of the circuit based on a signal from the DC coupling arrangement. 10. A solid state lighting device comprising an AC/DC converter circuit according to any preceding claim. 11. An electric
40、al power supply comprising an AC/DC converter circuit according to any preceding claim. Description:This invention relates to the field of converter circuits, and more particularly to an AC/DC converter circuit for driving solid state lighting devices and the like.It is known to employ AC/DC convert
41、er circuits in order to drive and control Solid State Lighting (SSL) devices, such as LED. With high volume production of SSL devices, there is a desire to reduce the cost of such circuits.Conventional AC/DC converter circuits employ simple Integrated Circuit (ICS) in combination with external compo
42、nents. To limit the associated cost of the components, it is preferable to minimize headroom in the thermal design of the circuit and the SSL device, and this may require accurate regulation of the drive current supplied to the SSL device.Also, for the purpose of energy conservation, good performanc
43、e of the circuit in terms of efficiency and Power Factor (PF) may be required.IC s containing an advanced algorithm to achieve a good PF and accurate drive current are available, but these are also expensive. Some existing low-cost driver solutions are known which address the drive current accuracy
44、requirement, but these do not achieve an adequate PF.A good PF is becoming more and more important, and places a strict requirement on driver solutions. For example, in the United States of Americas, the PF must be at least 0.7 for residential use and even 0.9 for commercial use.Typical AC/DC conver
45、ter circuits for driving a SSL device comprise a Buck, tapped-Buck, Buck-Boost or Fly back converter that, in every switching cycle, ramps up the current in an induction to an accurate predefined value and then releases the magnetic energy into the SSL load. Depending on the converter working in Bou
46、ndary Conduction Mode (BCM) or Discontinuous Conduction Mode (DCM), the next cycle is started right after the energy in the induction has vanished to zero (in BCM) or only after receiving a control trigger from a separate timer, running on a defined switching frequency (in DCM).The most simple and l
47、ow-cost converter with a good performance in terms of drive current accuracy or regulation (assess able in terms of the insensitivity of the drive current to the magnitude of: the AC input voltage (e.g. a mains input voltage); the load voltage; induction value; and switching frequency FSW) is the Bu
48、ck converter operating in BCM. However, other circuits may be configured as Buck-Boost or Fly back driver working in BCMIn order to get a high PF, the switching frequency FSW and/or the convert input current IPK may be modulated with the phase of the input voltage (mains frequency being typically 50
49、 or 60Hz for example). However, known methods to modulate the converter input current and/or the switching frequency in this way are dependent on the magnitude of the input voltage, and result in a poor regulation of the drive current. This problem of poor regulation of the drive current (also referred to as line regulation) ha