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1、VHDL程序设计数字电子表(1),1,第六章 VHDL综合应用,数字电子时钟显示电路,VHDL程序设计数字电子表(1),2,6 个七段数码管,SEGOUT ( 8 ),CLR,时钟显示 电路方框图,CP,FPGA,SELOUT ( 6 ),VHDL程序设计数字电子表(1),3,24 进 制 计数器,60 进 制 计数器,60 进 制 计数器,BCD 七段译码电路,BCD 选择,BCD(8)BIN(6),6 个七段数码管,扫描电路 S(3),SEG (8),NUM(4),BCD (3-0),BCD (7-4),ENB (0),ENB (1),ENB (2),DBH,DBM,DBS,BIN ( 6
2、 ),时钟显示 电路方框图,SEC,CLR,CYH,CYS,CYM,分频器Q,CP,38 译 码,VHDL程序设计数字电子表(1),4,24 进 制 计数器,60 进 制 计数器,60 进 制 计数器,BCD 七段译码电路,BCD 选择,BCD(8)BIN(6),6 个七段数码管,扫描电路 S(3),SEG (8),NUM(4),BCD (3-0),BCD (7-4),ENB (0),ENB (1),ENB (2),DBH,DBM,DBS,BIN ( 6 ),时钟显示 电路方框图,SEC,CLR,CYH,CYS,CYM,分频器Q,CP,38 译 码,VHDL程序设计数字电子表(1),5,PRO
3、CESS (CP) Begin IF CPEvent AND CP=1 then DLY = Q(21); Q = Q+1; END IF; END PROCESS;,VHDL程序设计数字电子表(1),6,Free_Counter : Block Signal Q: STD_LOGIC_VECTOR(24 DOWNTO 0); Signal DLY : STD_LOGIC; Begin PROCESS (CP) Begin IF CPEvent AND CP=1 then DLY = Q(21); Q = Q+1; END IF; END PROCESS; SEC = Q(21) AND NO
4、T DLY;-about 1Hz S = Q(15 DOWNTO 13);-about 250 Hz ENB = 001 WHEN (S=0 OR S=1) ELSE 010 WHEN (S=2 OR S=3) ELSE 100 WHEN (S=4 OR S=5) ELSE 000; BIN = DBS WHEN ENB = 001 ELSE DBM WHEN ENB = 010 ELSE DBH WHEN ENB = 100 ELSE 000000; End Block Free_Counter;,VHDL程序设计数字电子表(1),7,-主文件声明代码 COMPONENT COUNTER60
5、 PORT( CP: INSTD_LOGIC; BIN: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0); S: INSTD_LOGIC; CLR: IN STD_LOGIC; EC: IN STD_LOGIC; CY60: OUT STD_LOGIC ); END COMPONENT;,VHDL程序设计数字电子表(1),8,- 子文件定义代码 -* LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -* ENTITY COUNTER60 IS PORT( CP : IN STD_LOGIC; BIN: OUT STD_LOGIC_
6、VECTOR (5 DOWNTO 0); S : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY60 : OUT STD_LOGIC ); END COUNTER60;,VHDL程序设计数字电子表(1),9,- 子文件定义代码 ARCHITECTURE a OF COUNTER60 IS SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC; BEGIN PROCESS (CP,RST) BEGIN IF RST = 1 THEN Q = 00
7、0000; ELSIF CPevent AND CP = 1 THEN DLY = Q(5); IF EC = 1 THEN Q = Q+1; END IF; END IF; END PROCESS; CY60 = NOT Q(5) AND DLY; RST = 1 WHEN Q=60 OR CLR=1 ELSE 0; BIN = Q WHEN S = 1 ELSE 000000; END a;,VHDL程序设计数字电子表(1),10,-主文件声明代码 COMPONENT COUNTER24 PORT( CP: INSTD_LOGIC; BIN: OUTSTD_LOGIC_VECTOR (5
8、DOWNTO 0); S: INSTD_LOGIC; CLR: IN STD_LOGIC; EC: IN STD_LOGIC; CY60: OUT STD_LOGIC ); END COMPONENT;,VHDL程序设计数字电子表(1),11,- 子文件定义代码 -* LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -* ENTITY COUNTER24 IS PORT( CP : IN STD_LOGIC; BIN: OUT STD_LOGIC_VECTOR (5 DOWNTO 0); S
9、 : IN STD_LOGIC; CLR : IN STD_LOGIC; EC : IN STD_LOGIC; CY24 : OUT STD_LOGIC ); END COUNTER24;,VHDL程序设计数字电子表(1),12,- 子文件定义代码 ARCHITECTURE a OF COUNTER24 IS SIGNAL Q : STD_LOGIC_VECTOR (4 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC; BEGIN PROCESS (CP,RST) BEGIN IF RST = 1 THEN Q = 00000; ELSIF CPevent AN
10、D CP = 1 THEN DLY = Q(4); IF EC = 1 THEN Q = Q+1; END IF; END IF; END PROCESS; CY24 = NOT Q(4) AND DLY; RST = 1 WHEN Q=24 OR CLR=1 ELSE 0; BIN = (0 ,VHDL程序设计数字电子表(1),13,Binary_BCD : Block BEGIN BCD =00000000 WHEN BIN = 0 ELSE 00000001 WHEN BIN = 1 ELSE 00000010 WHEN BIN = 2 ELSE 00000011 WHEN BIN =
11、3 ELSE 00000100 WHEN BIN = 4 ELSE 00000101 WHEN BIN = 5 ELSE 00000110 WHEN BIN = 6 ELSE 00000111 WHEN BIN = 7 ELSE 00001000 WHEN BIN = 8 ELSE 00001001 WHEN BIN = 9 ELSE 00010000 WHEN BIN = 10 ELSE 00010001 WHEN BIN = 11 ELSE 00010010 WHEN BIN = 12 ELSE 00010011 WHEN BIN = 13 ELSE 00010100 WHEN BIN =
12、 14 ELSE 00010101 WHEN BIN = 15 ELSE 00010110 WHEN BIN = 16 ELSE 00010111 WHEN BIN = 17 ELSE 00011000 WHEN BIN = 18 ELSE 00011001 WHEN BIN = 19 ELSE 00100000 WHEN BIN = 20 ELSE 00100001 WHEN BIN = 21 ELSE 00100010 WHEN BIN = 22 ELSE 00100011 WHEN BIN = 23 ELSE 00100100 WHEN BIN = 24 ELSE 00100101 WH
13、EN BIN = 25 ELSE 00100110 WHEN BIN = 26 ELSE 00100111 WHEN BIN = 27 ELSE,VHDL程序设计数字电子表(1),14,00101000 WHEN BIN = 28 ELSE 00101001 WHEN BIN = 29 ELSE 00110000 WHEN BIN = 30 ELSE 00110001 WHEN BIN = 31 ELSE 00110010 WHEN BIN = 32 ELSE 00110011 WHEN BIN = 33 ELSE 00110100 WHEN BIN = 34 ELSE 00110101 WH
14、EN BIN = 35 ELSE 00110110 WHEN BIN = 36 ELSE 00110111 WHEN BIN = 37 ELSE 00111000 WHEN BIN = 38 ELSE 00111001 WHEN BIN = 39 ELSE 01000000 WHEN BIN = 40 ELSE 01000001 WHEN BIN = 41 ELSE 01000010 WHEN BIN = 42 ELSE 01000011 WHEN BIN = 43 ELSE 01000100 WHEN BIN = 44 ELSE 01000101 WHEN BIN = 45 ELSE 010
15、00110 WHEN BIN = 46 ELSE 01000111 WHEN BIN = 47 ELSE 01001000 WHEN BIN = 48 ELSE 01001001 WHEN BIN = 49 ELSE 01010000 WHEN BIN = 50 ELSE 01010001 WHEN BIN = 51 ELSE 01010010 WHEN BIN = 52 ELSE 01010011 WHEN BIN = 53 ELSE 01010100 WHEN BIN = 54 ELSE 01010101 WHEN BIN = 55 ELSE 01010110 WHEN BIN = 56
16、ELSE 01010111 WHEN BIN = 57 ELSE 01011000 WHEN BIN = 58 ELSE 01011001 WHEN BIN = 59 ELSE 00000000; END Block Binary_BCD;,VHDL程序设计数字电子表(1),15,SELECT_BCD : Block BEGIN NUM = BCD(3 DOWNTO 0) WHEN (S=0 OR S=2 OR S=4) ELSE BCD(7 DOWNTO 4); End Block SELECT_BCD;,VHDL程序设计数字电子表(1),16,SEVEN_SEGMENT : Block B
17、egin -gfedcba SEG = 0111111 WHEN NUM = 0 ELSE 0000110 WHEN NUM = 1 ELSE 1011011 WHEN NUM = 2 ELSE 1001111 WHEN NUM = 3 ELSE 1100110 WHEN NUM = 4 ELSE 1101101 WHEN NUM = 5 ELSE 1111101 WHEN NUM = 6 ELSE 0000111 WHEN NUM = 7 ELSE 1111111 WHEN NUM = 8 ELSE 1101111 WHEN NUM = 9 ELSE 1110111 WHEN NUM = 1
18、0 ELSE 1111100 WHEN NUM = 11 ELSE 0111001 WHEN NUM = 12 ELSE 1011110 WHEN NUM = 13 ELSE 1111001 WHEN NUM = 14 ELSE 1110001 WHEN NUM = 15 ELSE 0000000; End Block SEVEN_SEGMENT;,VHDL程序设计数字电子表(1),17,延迟与微分电路,用途：将宽脉冲减小为一个时钟周期的脉 冲宽度；消除小于一个周期的脉冲,VHDL程序设计数字电子表(1),18,机械开关的抖动存在三种情况：按下时有抖动，松开时也有抖动；按下时有抖动，松开时无抖
19、动；按下时无抖动，松开时有抖动。机械开关的抖动波形、抖动次数、抖动时间都是随机的，并不是每次都会产生抖动。 不同开关的最长抖动时间也不同。抖动时间的长短和机械开关特性有关，一般为5ms到10ms。但是，某些开关的抖动时间长达20ms，甚至更长。所以，在具体设计中要具体分析，根据实际情况来调整设计。 弹跳现象以及弹跳消除如图1 所示，虽然只是按下按键一次后放掉，结果在按键信号稳定先后竟出现了多个段脉冲，如果将这样的信号直接送到计数器之类的时序电路，结果将可能发生计数超过一次以上的误动作，从而误以为键盘按了多次。因此，必须加上弹跳消除电路，除去短脉冲，避免误操作的发生。,按键消抖电路,VHDL程序
20、设计数字电子表(1),19,消抖电路,用途：消除竞争冒险；消除抖动,VHDL程序设计数字电子表(1),20,延时比较法或积分法 比较法：这个方法很好理解，就是若干个时钟周期读取的数据相同时我们认为收到了一个稳定的数据，否则认为是过渡态。即采用若干位的移位寄存器，当寄存器是全1或全0时才开始读数。这种方法的缺点是，当干扰脉冲较宽时我们必须等比地扩大移位寄存器的比特，消耗较大资源。,VHDL程序设计数字电子表(1),21,消抖电路,VHDL程序设计数字电子表(1),22,-* LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC
21、_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -* ENTITY Debunce is PORT( test_S: OUT STD_LOGIC; CP: IN STD_LOGIC; Key : IN STD_LOGIC; DLY_OUT : OUT STD_LOGIC; DIF_OUT: OUT STD_LOGIC ); END Debunce; -* ARCHITECTURE a OF Debunce IS,VHDL程序设计数字电子表(1),23,SIGNAL SAMPLE, DLY, NDLY, DIFF: STD_LOGIC;- Binary
22、BEGIN test_S 25HZ脉冲 -SAMPLE = Q(1) AND NOT D0; END Block Free_Counter;,VHDL程序设计数字电子表(1),24,Debunce : Block- Debounce SIGNAL D0, D1, S, R : STD_LOGIC; Begin Process (CP) Begin IF CPEVENT AND CP=1 THEN IF SAMPLE = 1 THEN D1 = D0; D0 = KEY;- Two Stage Delay S = D0 AND D1;- Generate S、R R = NOT D0 AND N
23、OT D1; END IF; END IF; End Process; DLY = R NOR NDLY;- Debounce O/P NDLY =S NOR DLY; DLY_OUT = DLY; End Block Debunce;,VHDL程序设计数字电子表(1),25,Differential : Block-Differential Signal D1,D0 : STD_LOGIC; BEGIN Process (CP) Begin IF CPEVENT AND CP=1 THEN D1 = D0; D0 = DLY;- Two State Delay END IF; End Pro
24、cess; DIFF = D0 AND NOT D1;- Differential END Block Differential; DIF_OUT = DIFF;- Differential O/P END a;,VHDL程序设计数字电子表(1),26,延迟与微分电路,时序图：,CP,IN,Q1,Q2,OUT,VHDL程序设计数字电子表(1),27,同步计数器电路,用途：消除竞争冒险；消除延时误差,VHDL程序设计数字电子表(1),28,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENT
25、ITY Timer_Dsp is PORT( CP: IN STD_LOGIC; SEGOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SELOUT: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); CLEAR : IN STD_LOGIC ); END Timer_Dsp; ARCHITECTURE a OF Timer_Dsp IS COMPONENT COUNTER60 PORT( CP: INSTD_LOGIC; BIN: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0); S: INSTD_LOGIC; CLR: IN
26、 STD_LOGIC; EC: IN STD_LOGIC; CY60: OUT STD_LOGIC ); END COMPONENT; COMPONENT COUNTER24 PORT( CP: INSTD_LOGIC; BIN: OUTSTD_LOGIC_VECTOR (5 DOWNTO 0); S: INSTD_LOGIC; CLR: IN STD_LOGIC; EC: IN STD_LOGIC; CY24: OUT STD_LOGIC ); END COMPONENT;,VHDL程序设计数字电子表(1),29,SIGNAL BIN : STD_LOGIC_VECTOR (5 DOWNTO
27、 0); SIGNAL DBS : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL DBM : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL DBH : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL ENB : STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL SEC: STD_LOGIC; SIGNAL BCD : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL CLR: STD_LOGIC; SIGNAL CYS,CYM,CYH: STD_LOGIC
28、; Signal S : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL NUM : STD_LOGIC_VECTOR( 3 DOWNTO 0); SIGNAL SEG: STD_LOGIC_VECTOR( 6 DOWNTO 0); BEGIN,VHDL程序设计数字电子表(1),30,Connection : Block Begin U1: COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,SEC,CYS); U2: COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,CYS,CYM); U3: COUNTER24 POR
29、T MAP(CP,DBH,ENB(2),CLR,CYM,CYH); CLR = CLEAR; SELOUT = S; SEGOUT(6 DOWNTO 0) = SEG; SEGOUT(7) = 0; End Block Connection;,VHDL程序设计数字电子表(1),31,Free_Counter : Block Signal Q: STD_LOGIC_VECTOR(24 DOWNTO 0); Signal DLY : STD_LOGIC; Begin PROCESS (CP)- 计数器计数 Begin IF CPEvent AND CP=1 then DLY = Q(21); Q
30、= Q+1; END IF; END PROCESS; SEC = Q(21) AND NOT DLY;-about 1Hz S = Q(15 DOWNTO 13);-about 250 Hz ENB = 001 WHEN (S=0 OR S=1) ELSE 010 WHEN (S=2 OR S=3) ELSE 100 WHEN (S=4 OR S=5) ELSE 000; BIN = DBS WHEN ENB = 001 ELSE DBM WHEN ENB = 010 ELSE DBH WHEN ENB = 100 ELSE 000000; End Block Free_Counter;,V
31、HDL程序设计数字电子表(1),32,Binary_BCD : Block BEGIN BCD =00000000 WHEN BIN = 0 ELSE 00000001 WHEN BIN = 1 ELSE 00000010 WHEN BIN = 2 ELSE 00000011 WHEN BIN = 3 ELSE 00000100 WHEN BIN = 4 ELSE 00000101 WHEN BIN = 5 ELSE 00000110 WHEN BIN = 6 ELSE 00000111 WHEN BIN = 7 ELSE 00001000 WHEN BIN = 8 ELSE 00001001
32、 WHEN BIN = 9 ELSE 00010000 WHEN BIN = 10 ELSE 00010001 WHEN BIN = 11 ELSE 00010010 WHEN BIN = 12 ELSE 00010011 WHEN BIN = 13 ELSE 00010100 WHEN BIN = 14 ELSE 00010101 WHEN BIN = 15 ELSE 00010110 WHEN BIN = 16 ELSE 00010111 WHEN BIN = 17 ELSE 00011000 WHEN BIN = 18 ELSE 00011001 WHEN BIN = 19 ELSE 0
33、0100000 WHEN BIN = 20 ELSE 00100001 WHEN BIN = 21 ELSE 00100010 WHEN BIN = 22 ELSE 00100011 WHEN BIN = 23 ELSE 00100100 WHEN BIN = 24 ELSE 00100101 WHEN BIN = 25 ELSE 00100110 WHEN BIN = 26 ELSE 00100111 WHEN BIN = 27 ELSE 00101000 WHEN BIN = 28 ELSE 00101001 WHEN BIN = 29 ELSE,VHDL程序设计数字电子表(1),33,0
34、0110000 WHEN BIN = 30 ELSE 00110001 WHEN BIN = 31 ELSE 00110010 WHEN BIN = 32 ELSE 00110011 WHEN BIN = 33 ELSE 00110100 WHEN BIN = 34 ELSE 00110101 WHEN BIN = 35 ELSE 00110110 WHEN BIN = 36 ELSE 00110111 WHEN BIN = 37 ELSE 00111000 WHEN BIN = 38 ELSE 00111001 WHEN BIN = 39 ELSE 01000000 WHEN BIN = 4
35、0 ELSE 01000001 WHEN BIN = 41 ELSE 01000010 WHEN BIN = 42 ELSE 01000011 WHEN BIN = 43 ELSE 01000100 WHEN BIN = 44 ELSE 01000101 WHEN BIN = 45 ELSE 01000110 WHEN BIN = 46 ELSE 01000111 WHEN BIN = 47 ELSE 01001000 WHEN BIN = 48 ELSE 01001001 WHEN BIN = 49 ELSE 01010000 WHEN BIN = 50 ELSE 01010001 WHEN
36、 BIN = 51 ELSE 01010010 WHEN BIN = 52 ELSE 01010011 WHEN BIN = 53 ELSE 01010100 WHEN BIN = 54 ELSE 01010101 WHEN BIN = 55 ELSE 01010110 WHEN BIN = 56 ELSE 01010111 WHEN BIN = 57 ELSE 01011000 WHEN BIN = 58 ELSE 01011001 WHEN BIN = 59 ELSE 00000000; END Block Binary_BCD;,VHDL程序设计数字电子表(1),34,SELECT_BC
37、D : Block BEGIN NUM Segment 7 Code Begin -gfedcba SEG = 0111111 WHEN NUM = 0 ELSE 0000110 WHEN NUM = 1 ELSE 1011011 WHEN NUM = 2 ELSE 1001111 WHEN NUM = 3 ELSE 1100110 WHEN NUM = 4 ELSE 1101101 WHEN NUM = 5 ELSE 1111101 WHEN NUM = 6 ELSE 0000111 WHEN NUM = 7 ELSE 1111111 WHEN NUM = 8 ELSE 1101111 WHEN NUM = 9 ELSE 1110111 WHEN NUM = 10 ELSE 1111100 WHEN NUM = 11 ELSE 0111001 WHEN NUM = 12 ELSE 1011110 WHEN NUM = 13 ELSE 1111001 WHEN NUM = 14 ELSE 1110001 WHEN NUM = 15 ELSE 0000000; End Block SEVEN_SEGMENT; END a;,