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1、Operating System,Chapter 2: Basic Concept and Prerequisite knowledge GuangShun Shi Department of Computer Science, NanKai University Email: Web Site: http:/202.113.15.72/osteach,Computer Hardware Review,Processors: Architecture and Modes Memory: Hierarchy of storage systems I/O Devices: Clock, keyb
2、oard, monitor and hard disk Buses: Organization of computer system,Operating System,CITS, NanKai University,2,History of Processors,The beginning of microprocessor 1960s, Intel 4004 1983, Intel 80286 16bits, 1MB address space, 20K instructions, 2.5MIPS & 4.0MIPS 32 bit & 64 bit microprocessor Intel
3、80386(1986), Intel 80486(1989), Intel Pentium(1993) 32bits, 4GB address space, CISC & RISC, xGIPS 64bits, 64PB address space,Operating System,CITS, NanKai University,3,Structure of microprocessor,Execute unit Execute the specified instruction Control unit Fetch instruction from memory to registers M
4、aintain the status of CPU Data transfer between CPU and memory Register and Cache Pipeline,Operating System,CITS, NanKai University,4,Instruction cycle of processor,Fetch instruction from memory Program Counter stores the address of next instruction Processor fetch the instruction via memory access
5、Decode instruction Store the parameters of the instruction into registers Execute instruction Instruction Register stores current instructions Integer, float and Boolean processors Pipeline Sequence of circuit units to execute an instruction,Operating System,CITS, NanKai University,5,Start,Fetch uni
6、t,Decode unit,Execute unit,End,Guide line of processors capability,Frequency CPU clock speed = CPU socket speed * clock multiplier CPU socket speed: the times per second that transfer data from/to CPU, generated by mainboard Front side bus speed: the bandwidth that transfer data between “Northbridge
7、” chip and CPU Clock multiplier Memory clock speed Instruction set & Coprocessor CISC, RISC, EPIC Float processor, Boolean processor Cache Level1& Level 2 cache: registers & buffers Architecture Micro-architecture, Superscalar & super-pipeline Technics 45 nm: the nearest progress of processor design
8、ing,Operating System,CITS, NanKai University,6,Class examination,Assumption CPU word length = 64 bit Data transfer speed requirement:800 Mbytes / second Please calculate the front side bus speed Answer 800Mbytes = FSB speed (MHZ) * 64 / 8 FSB speed = 100MHZ,Operating System,CITS, NanKai University,7
9、,Architecture of processor,Operating System,CITS, NanKai University,8,Superscalar and super-pipeline,Operating System,CITS, NanKai University,9,Fetch unit,Decode unit,Execute unit,Fetch unit,Decode unit,Execute unit,Execute unit,Holding Buffer,Superscalar pipeline,Operating System,CITS, NanKai Unive
10、rsity,10,Architecture of processor,Operating System,CITS, NanKai University,11,Registers in CPU,Address register Store the address of data or instruction Data register Store the operand/operator of instruction Flag register Store the flags of operation Control and status register Used by OS for mana
11、ging CPU,Operating System,CITS, NanKai University,12,Registers in CPU (privileged),Program counter The register that stores address of next instruction Each process has its private PC value Instruction register Stores the instruction to be executed Each process has its private IC value Program statu
12、s word The register that stores flags and conditions of CPU working status PSW is the most important part of CPU context,Operating System,CITS, NanKai University,13,Essential of CPU,Rank of CPU instruction R0: privileged instruction only used by OS R1: important device driver and I/O routine R2: pro
13、tected program, such as IDE R3: user space for common program Working mode of CPU Kernel mode & User mode “Trap” Switch the mode of CPU from “user” mode to “kernel” mode,Operating System,CITS, NanKai University,14,Essential of CPU,Operating System,CITS, NanKai University,15,Proc 1,Instruction regist
14、er,Program counter,Program status word,PU,Proc 2,Instruction register,Program counter,Program status word,PSW of Intel CPU,Operating System,CITS, NanKai University,16,CF： 进位标志位 ZF： 结果为零标志位 SF： 符号标志位 OF： 溢出标志位,标准条件位： TF：陷阱标志位 IF：中断允许（中断屏蔽）标志位 VIF：虚拟中断标志位 VIP：虚拟中断待决标志位 IOPL：IO特权级别,Clock and clock inte
15、rrupts,Operating System,CITS, NanKai University,17,每个脉冲使计数器减1，归零则产生时钟中断,用来装入计数器初值,Clock in computer,What dose time means in computer The speed of operation and execution The criterion of resource management The bandwidth of data transfer The record of real time Components of programmable clock Cryst
16、al oscillator: physical component Counter: decremented at each pulse Holding register: record the initial value of counter One-shot clock and square-wave clock One-shot clock: controlled by OS software Square-wave clock: generate periodic signal Clock tick: periodic interrupts,Operating System,CITS,
17、 NanKai University,18,Operating System,CITS, NanKai University,19,Essential of Interruption,Operating System,CITS, NanKai University,20,Essential of Interruption,Operating System,CITS, NanKai University,21,Essential of Interruption (unnested),Operating System,CITS, NanKai University,22,Essential of
18、Interruption (nested),低优先级中断嵌套高优先级中断的处理流程,Operating System,CITS, NanKai University,23,Essential of Interruption,Interrupt, Exception and trap,Exception Errors found by hardware, caused by program Divide by 0, floating-point underflow, access denied The exception will be handled by OS in kernel mode,
19、 or informed to the program and handled by user program Interrupt Signal sent from hardware to CPU CPU finds and invokes interrupt handler (kernel mode) In time-sharing OS, the interrupts are handled in clock interrupt function System call Interface provided by OS to allow programs obtaining some sy
20、stem service “Trap” instruction will trap into kernel mode and invoked OS to execute service,Operating System,CITS, NanKai University,24,Operating System,CITS, NanKai University,25,Storage system in computer,Operating System,CITS, NanKai University,26,Strategy of storage system,Guide lines for stora
21、ge system Speed: should be not slower than CPU speed Size: should be enough large that can store everything Cost: should not be expensive for most customers Strategy for a reasonable storage system Local optimal principle Hierarchy architecture Various kinds of memory Register, RAM, SRAM, DRAM, SDRA
22、M, DDR ROM, PROM, EPROM, EEPROM, CMOS Flash memory,Operating System,CITS, NanKai University,27,Local optimal principle,A story about Yangguo and Xiaolongnv The answer exists around the question Local optimal principle in address space The address of next instruction should be adjacent to current ins
23、truction Local optimal principle in time sequence The instruction used recently should be used again in the near future Principle of Cache design Only stores the instructions that belong to a local region, both in address space and time sequence Small size and slow speed, but higher performance and
24、cheap price,Operating System,CITS, NanKai University,28,Local optimal principle,Operating System,CITS, NanKai University,29,Architecture of Computer,Operating System,CITS, NanKai University,30,North bridge and south bridge,North bridge Transfer data between CPU and memory/AGP More expensive, faster
25、and complicated South bridge Transfer data between I/O buses and devices Cheap, slow and cheap The communication between I/O and CPU CPU dont access I/O device directly Some special mechanisms are designed for the link between north bridge and south bridge (DMA, I/O channel) Intel Hub Architecture, SIS Multithread(妙渠),Operating System,CITS, NanKai University,31,Operating System,CITS, NanKai University,32,Thanks for your time! Questions & Answers,