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1、 PES331 ADC-Type Enhanced Field Programmable Processor Array (FPPATM) Data Sheet Preliminary Version 0.53 Sep. 7, 2012 Copyright 2012 by PADAUK Technology Co., Ltd., all rights reserved 10F-2, No. 1, Sec. 2, Dong-Da Road, Hsin-Chu 300, Taiwan, R.O.C. TEL: 886-3-532-7598 .tw PES331 ADC-Type Enhanced
2、FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 2 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 IMPORTANT NOTICE PADAUK Technology reserves the right to make changes to its products or to terminate production of its products with notice one year in advance. PADAUK Technology products are no
3、t warranted to be suitable for use in life-support applications or other critical applications. PADAUK Technology assumes no liability for such applications. Critical applications include, but are not limited to, those that may involve potential risks of death, personal injury, fire or severe proper
4、ty damage. PADAUK Technology assumes no responsibility for any issue caused by a customers product design. Customers should design and verify their products within the ranges guaranteed by PADAUK Technology. In order to minimize the risks in customers products, customers should design a product with
5、 adequate operating safeguards. PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 3 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Table of Contents Features7 High Performance RISC CPU Array .7 System functions.7 General Description and Block Diagram8 Pin Assignment an
6、d Pin Description .9 Device Characteristics.11 DC Characteristics11 AC Characteristics12 Absolute Maximum Ratings 12 Typical operating frequency vs. VDD12 Typical measurement of IO driving current V=VDD*0.9 OH 13 Typical measurement of IO driving current V=VDD*0.5 OH 13 Typical measurement of IO sin
7、k current V=VDD*0.1 OL .14 Typical measurement of IO sink current V=VDD*0.5 OL .14 Typical measurement of IO input threshold voltage (input low to high).15 Typical measurement of IO input threshold voltage (input high to low).15 Typical measurement of operating current vs. VDD and frequency (IHRC)16
8、 Typical measurement of operating current vs. VDD and frequency (ILRC) 16 Typical measurement of IHRC frequency vs. VDD.17 Typical measurement of IHRC frequency vs. temperature .17 Typical measurement of ILRC frequency vs. VDD18 Typical measurement of IO pull high resistance .18 Package Power Dissip
9、ation V.S. Ambient Temperature19 Functional Description20 Processing Units.20 Program Counter 20 Program Memory - OTP 20 Stack Pointer 20 Arithmetic and Logic Unit21 Program Sequencer21 16-bit Timer.21 Oscillator and clock.21 External RC Oscillator.22 PES331 ADC-Type Enhanced FPPATM Controller Copyr
10、ight 2012, PADAUK Technology Co. Ltd Page 4 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Crystal Oscillator.22 External Clock Source.23 Watchdog Timer23 Interrupt 24 Power Saving24 IO Pins24 Reset 25 Power-On-Reset (POR).25 Low-Voltage-Detector (LVD).25 Analog-to-Digital Conversion (ADC) module.26 The inpu
11、t requirement for AD conversion.27 Selecting the ADC bit resolution.28 ADC clock selection28 AD conversion.28 Configuring the analog pins.28 IO Registers Address and Description.29 The address mapping of IO registers is the following: 29 ACC Status Flag Register (flag), IO address = 0x00 30 FPP unit
12、 Enable Register (fppen), IO address = 0x0130 Stack Pointer Register (sp), IO address = 0x0230 Clock Mode Register (clkmd), IO address = 0x03.30 Interrupt Enable Register (inten), IO address = 0x0431 Interrupt Request Register (intrq), IO address = 0x0531 Timer 16 mode Register (t16m), IO address =
13、0x06.31 General Data register for IO (gdio), IO address = 0x07 32 External Oscillator setting Register (eoscr), IO address = 0x0a32 Internal High RC oscillator control Register low (ihrcr), IO address = 0x0b 32 Port A, B Data Registers (pa, pb), IO address = 0x10, 0x14.32 Port A, B Control Registers
14、 (pac, pbc), IO address = 0x11, 0x15.32 Port A, B Pull-High Registers (paph, pbph), IO address = 0x12, 0x1633 Port A Open-Drain Registers (paod), IO address = 0x1333 ADC Control Register (adcc), IO address = 0x20.33 ADC Mode Register (adcm), IO address = 0x21.33 ADC Result High Register (adcrh), IO
15、address = 0x22.34 ADC Result Low Register (adcrl), IO address = 0x23.34 Analog Input Control Register (adcdi), IO address = 0x2434 PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 5 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Instructions 35 Data Transfer Instructi
16、ons (20) .36 Arithmetic Operation Instructions (19).41 Shift Operation Instructions (10) .43 Logic Operation Instructions (16)44 Bit Operation Instructions (6) 47 Conditional Operation Instructions (13).48 System control Instructions (18) .50 Summary of Instructions Execution Cycle.53 Summary of aff
17、ected flags by Instructions54 3-Phase Brushless DC Motor application55 Key Features: .55 Functional Block Diagram:55 Functional Description: .56 Application Diagram:.57 Package and Marking Information60 Marking Information60 SSOP20 Package Information60 PES331 ADC-Type Enhanced FPPATM Controller Cop
18、yright 2012, PADAUK Technology Co. Ltd Page 6 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Revision History: Revision Date Description 0.10 2009/7/28 1st version 0.20 2009/9/24 Combine 3-phase Brushless Motor controller and MCU functions 0.30 2010/2/6 1. Add VOL, VOH 2. Add Chart of Package Power Dissipati
19、on 0.40 2010/5/13 1. Modify important notice 2. Package information 0.42 2010/7/26 Modify application circuit 0.50 2011/4/8 Amend IHRC vs Temp measurement chart and characteristic 0.52 2012/1/3 Amend Thermal Operating Conditions 0.53 2012/9/7 Amend part of 3-Phase Brushless DC Motor application PES3
20、31 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 7 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Features High Performance RISC CPU Array Patent Pending Field Programmable Processor Array (FPPA) Technology 8x8 processor array with parallel processing capability 102 power
21、ful instructions 2KW OTP program memory for all FPP units 192 bytes data memory All instructions are 1T except indirect memory access One cycle for branch instructions to reduce overhead Programmable stack pointer / adjustable stack level Direct / indirect addressing modes for data and instructions
22、Bit-manipulation instructions All data memories are available for use as an index pointer Support security function to protect OTP data Separated IO space and memory space Powerful instructions for peripheral functions Powerful instructions for intra-FPP handshaking System functions Clock sources: i
23、nternal high RC, internal low RC, external RC, external crystal and external clock Built-in internal high RC oscillator Built-in Power On Reset and Low Voltage Detector One hardware 16-bit timer Two channels 12-bit ADC Support software full duplex UART Support software flexible PWM waveform generati
24、on Support software SPI serial protocol 10-pin MSOP10 package 7 IO pins and 1 input pin IO pins with 15mA capability Operating voltage range fSYS= 16MHz5.0V fSYS= 8MHz3.3V Maximum performance Crystal mode: 16MIPSVDD=5.0V Internal High RC Mode: 16MIPSVDD=5.0V Operating voltage range: 2.5V 5.5V Operat
25、ing temperature range: -40C 85C Operating frequency range Crystal mode: DC 16MHzVDD=5.0V DC 8MHzVDD=3.3V Internal High RC Mode: DC 16MHzVDD=5.0V DC 8MHzVDD=3.3V Low power consumption Ioperating 1.2mA1MIPS / VDD=5.0V Ioperating 7uA VDD=3.3V, use ILRC 19KHz Istandby 0.6uAVDD=5.0V Istandby 0.2uAVDD=3.3
26、V PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 8 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 General Description and Block Diagram The PES331 is an ADC-Type of PADAUKs parallel processing, fully static, OTP-based CMOS 8x8 processor array that can execute numero
27、us peripheral functions in parallel. It employs RISC architecture based on patent pending FPPA (Field Programmable Processor Array) technology and all the instructions are executed in one cycle except that some instructions are two cycles that handle indirect memory access. Two channels 12-bit ADC i
28、s also built inside the chip. By using FPPA technology, it allows most of peripheral functions to be performed by software to meet customers requirements in different applications. The parallel processing architecture provides a system true real-time multi-tasking capability by hardware approach. 12
29、-bit ADC POR / LVD WatchDog Timer FPP5 FPP6 FPP7 Task Management FPP0 FPP1 FPP2 FPP3 FPP4 Interrupt Controller 16-bit Timer IO ports SRAM PWM Function Power Management I2C Function SPI Function UART Function Key Scan Function FPP array address bus FPP array data bus Task Bank IR receive Function FPP
30、 array control bus Peripheral address bus Peripheral data bus Peripheral control bus PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 9 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Pin Assignment and Pin Description Pin Description for PES331 Pin No. Pin Name Descri
31、ption 18 PA7/NC/X1 This pin can be used as (1) Bit 7 of port A when an internal RC oscillator is used and can be configured as input/output, with pull-up resistor, open-drain output mode by software. (2) Leave this pin no connection when an external clock oscillator is used. (3) X1 when a crystal os
32、cillator or an external RC oscillator is used. 17 PA6/CKIN/X2 This pin can be used as (1) Bit 6 of port A when an external crystal oscillator is not used and can be configured as input/output, with pull-up resistor, open-drain output mode by software. (2) Clock input when an external clock oscillato
33、r is used. (3) X2 when a crystal oscillator is used. 4 PA5/PRST# This input pin can be used as (1) hardware reset of this chip. (2) Bit 5 of port A. Please note that this pin is for input only and does not have pull-up or pull-down resistor. 3 PA4 2 PA3 1 PA2 20 PA1 Bit 4, 3, 2, and 1 of port A. The
34、se four pins can each be configured as input/output, with pull-up resistor, open-drain output mode by software. 19 PA0/INT0 Bit 0 of port A or external interrupt line 0. This pin can be configured as input/output, with pull-up resistor, open-drain output mode by software and can be used as an extern
35、al interrupt line 0. Both rising edge and falling edge are accepted to request interrupt service. 14 PB7/AD7 13 PB6/AD6 12 PB5/AD5 11 PB4/AD4 10 PB3/AD3 9 PB2/AD2 Bit 70 of port B or channel 70 of analog input. These eight pins can each be configured as analog input, digital input, two-states output
36、 mode with pull-up resistor independently by software and PB0/AD0/INT1 can be used as an external interrupt line, both rising edge and falling edge are accepted to request interrupt service. When any of these eight pins acts as analog inputs, it must be programmed as analog input via analog input co
37、ntrol register to avoid leakage current. (For general MCU application) 11 12 20 19 18 17 16 15 14 13 10 9 1 2 3 4 5 6 7 PA2PA1 PA0/INT0 PA3 PA7/NC/X1 PA4 PA6/CKIN/X2PA5/PRST# VDD GND AVDD AGND PB7/AD7 PB0/INT1/AD0 PB6/AD6 PB1/AD18 PB5/AD5 PB2/AD2 PB4/AD4 PB3/AD3 PES331 (SSOP20-150mil) PES331 ADC-Typ
38、e Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 10 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 8 PB1/AD1 7 PB0/AD0/INT1 16 VDD Digital Positive power 15 AVDD Analog Positive Power 5 GND Digital Ground 6 AGND Analog Ground PES331 ADC-Type Enhanced FPPATM Controller Copyright 201
39、2, PADAUK Technology Co. Ltd Page 11 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 Device Characteristics DC Characteristics Symbol Description Min Typ Max Unit Conditions (Ta=25) VDD Operating Voltage 2.5 5.0 5.5 V See operating freq. vs VDD chart IOP Operating Current 1.2 12 20 7 mA mA uA uA fSYS=1MIPS5.0
40、V fSYS=16MIPS5.0V fSYS=5.0V，use ILRC 32KHz fSYS=3.3V，use ILRC 19KHz IPD Power Down Current stack memory popw pc5 ; / pop the stack content to be the PC of FPP5 / request FPP5 to jump to “Codelabel” immediately Codelabel: - ldtabh index Load high byte data in OTP program memory to ACC by using index
41、as OTP address. It needs 2T to execute this instruction. Example: ldtabh index; Result: a bit 158 of OTP index; Affected flags: NZ NC NAC NOV Application Example: - word ROMptr ; / declare a pointer of ROM in RAM PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Pa
42、ge 39 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 mov a, laTableA ; / assign pointer to ROM TableA (LSB) mov lbROMptr, a ; / save pointer to RAM (LSB) mov a, haTableA ; / assign pointer to ROM TableA (MSB) mov hbROMptr, a ; / save pointer to RAM (MSB) ldtabh ROMptr ; / load TableA MSB to ACC (ACC=0X02) .
43、TableA : dc 0x0234, 0x0042, 0x0024, 0x0018 ; - ldtabl index Load low byte data in OTP to ACC by using index as OTP address. It needs 2T to execute this instruction. Example: ldtabl index; Result: a bit70 of OTP index; Affected flags: NZ NC NAC NOV Application Example: - word ROMptr ; / declare a poi
44、nter of ROM in RAM mov a, laTableA ; / assign pointer to ROM TableA (LSB) mov lbROMptr, a ; / save pointer to RAM (LSB) mov a, haTableA ; / assign pointer to ROM TableA (MSB) mov hbROMptr, a ; / save pointer to RAM (MSB) ldtabl ROMptr ; / load TableA LSB to ACC (ACC=0x34) . TableA : dc 0x0234, 0x004
45、2, 0x0024, 0x0018 ; - ldt16 word Move 16-bit counting values in Timer16 to memory in word. Example: ldt16 word; Result: word 16-bit timer Affected flags: NZ NC NAC NOV Application Example: - word T16val ; / declare a RAM word clear lb T16val ; / clear T16val (LSB) clear hb T16val ; / clear T16val (MSB) stt16 T16val ; / initial T16 with 0 set1 t16m.5 ; / enable Timer16 set0 t16m.5 ; / disable Timer 16 ldt16 T16val ; / save the T16 counting value to T16val . PES331 ADC-Type Enhanced FPPATM Controller Copyright 2012, PADAUK Technology Co. Ltd Page 40 of 60 PDK-DS-PES331_V053 Sep. 7, 2012 -