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1、3234bDD Ob77233 D U B EIA-IS/103-A October 1996 edif Electronic Design Interchange Format A DIVISION OF ELECTRONIC INDUSTRIES ASSOCIATION Library of Parameterized Modules Version 2 1 O Copyright Government Electronics for the compare primitive it is the assumed representation of the input (unsigned
2、or signed). The LPM standard specifies what values are valid for ail recognized properties. Any non-standard value for a standard property is considered an error. 2.2. i. 1 Legal Values for WM-“T Property The only exception to the above is the LPM-“T property. This optional property, which is attach
3、ed to instances of cell use, contains additional technology-specific information for use by the silicon vendor tools. There are no standard values for this field and it is there for the design tool vendors and the silicon tool vendors to utilize as needed. This property can always be ignored and the
4、 correct logic will be constructed, although the logic may not be constructed in the most efficient way. 2.2.2 Universal Properties Some properties apply to all LPM modules. Some of these properties are optional and some are required. Although these properties can be used with any module, they are n
5、ot described as one of the required or optional properties in the individual module descriptions. 2.2.2.1 Signal Polarities one bit for binary and four bits for hexadecimal. Examples: “-B- 1 1 1 1 “ - “B 1 1 1 1-“ “HEAD-“ “-HE-“ The “dont cares“ can take on any value for simulation. That is: undefin
6、ed, one or zero. The regular expressions for string values with dont cares in LPM: “-+?B-O1 A*“ “-+I? H -0-9 a-f A- F-*“ 2-5 Copyright Government Electronics the path must be routed through each storage element (or some of them, anyway) with no intervening logic. The scan testing strategy proceeds a
7、s follows: 1. Disable system.clwks (this includes any asynchronous sets or resets). 2. Apply the external test pattern on the Scan-In port and scan (shift) the test pattern in via the externally generated test clock (this clock can use the same wires as the system 3- 1 Copyright Government Electroni
8、cs ?x7 = C7 that is, if DataSel-Vue is not connected or is greater than LPM-Size, the selection of Sel Value will produce an undefined Result. 4.2.7.4 Example Suppose the designers have three 8-bit buses and they want to select one of the three buses. This is done using an LPM_MUX with an LPM-Width
9、of 8 and an LPMSize of three. The LPM-Width of eight indicates that there are eight multiplexers, and the LPM-Size of three indicates that each multiplexer has three inputs. . 4-15 Copyright Government Electronics if one is used, then using the other is an ERROR. . . . . 4-33 Copyright Government El
10、ectronics o0 small, some memory locations will not be addressable. If it is too big, then the addresses that are too high will return UNDEFINED. Note 2: If LPM-NumWords is not used, then it defaults to 2LPM-widtNLd. In general, this value should be (but is not required to be): 2LPM-wid*d-1 O LPM Val
11、ue O LPM Value O Width of input and output vectors. Width of Address Port. Note 1. Number of words stored in Memorv. Note 2. LPM-Width Ad Optional LPM-NumWords REGISTERED i UNREGISTERED registered. Default is Indicates if Data port is REGISTERED LPM-InData Optional LPM- Address-Contr o1 REGISTERED I
12、 UNREGISTERED Indicates if Address, MemEnab and WE ports are registered. Default is REGISTERED LPM-OutData LPM-File Optional Optional REGISTERED I UNREGISTERED Default is REGISTERED File Name Indicates if Q port is registered. File for RAM initialization. Note 1: The LPM-WidthAd should be (but is no
13、t required to be) equal to: riog2(LPM_NumWords)l. If LPM-WidthAd is too small, some memory locations will not be addressable. If is too big, then the addresses that are too high will return UNDEFINED. Note 2: If LPM-NurnWords is not used, then it defaults to 2 LPM-WidthAd. In general, this value sho
14、uld be (but is not required to be): 2 L p M _ w i d f h A d - O Required LPM Value O Optional LPM Value O Width of input and output vectors. Width of Address Port. Note 1. Number of words stored in Memory. Note 2. OutClock 4 LPM-Address-Control LPM-OutData tu Optional REGISTEED I Indicates if Addres
15、 port is Optional REGISTERED I Indicates if Q and Eq ports are UNREGISTERED registered. Default is REGISTERED UNREGISTERED registered. Default is REGISTERED 4.4.6.1 Ports Note 1: The Address is synchronous(registered) when the InClock port is connected. and asynchronous(registered) when it is not co
16、nnected Note 2: The addressed memory content + Q response is synchronous when the OutClock port is connected. and asynchronous when it is not connected. LPM-File I Required I FileName I File for ROM initialization. I 4-49 Copyright Government Electronics ! (direction OUTPUT) (port result3 (direction
17、 OUTPUT) (properly LPM-TYPE (string “LPM-ADD-SUB“) (property LPM-Width (integer 4) 1 ) 1 (cell FIBEX (cellType generic) (view schematic (viewType netlist) (interface (port CLEAR (direction INPUT) (port CLOCK (direction INPUT) (port (rename RESULT-91-0-93- “RESULTO“) (direction INOUT) (port (rename R
18、ESTJLT-91,1-93- “RESULT I“) (direction INOUT) (port (rename RESULT-91-2-93- “RESULT2“) (direction LNOT) (port (rename RESULT-9 1-3-93- “REsULT3“) (direction INOUT) 1 (contents (instance (rename 1-36-1 “I$1“) 1 (instance (rename 1-30 “I$3“) 1 (instance (rename 1-36-5 “I$5“) 1 (net CLEAR joined (viewR
19、ef viewl (CelRef dff-4) (viewRef view 1 (celiRef addsub-4) (viewRef view (CellRef dff-4) (portRef CLEAR) (portRef aset (instanceRef 1-36-1) 5-6 Copyright Government Electronics LPM in EDIF LPM2 1 O (cornplexName “Q“ (nameDimension (nameDimensionStructure 2) (pori 43 (outputport) (nameInformation (pr
20、imaryName “Q3“ (nameStructure (cornpiexName “Q“ (nameDimension (nameDimensionStnicture 3) (portElundle Q (portList poaef 43) (poaef Q2) (poruief Q 1) (poaef QW (nameInformation (primaryName “Q 3:O)“ (nameStructure (cornplexName “Q“ (nameDimension (nameDimensionStructure (sequence 3 0 ) ) ) ) ) ) ) )
21、 ) (property LPM-TYPE (string “LPM-F“) (property LPM-FFTYPE (string “DFF“) (property LPMWidth (integer 4) (property LPMAvaiue (integer I) (clusterHeader (cell addsub-4 (cellHeader (nameInformation (pnmaryName “addsub-4“) (cluster C 1 (interface (interfaceunits) (nameInformation (port DATAAO (inpupor
22、t) (primaryName “DATAAO“ (nameStructure (cornplexName “DATAA“ (nameDixnemion (nameDimensionStructure O) (port DATAAl (inputport) (nameInformation (primaryName “DATAA 1 “ (nameSucture (cornplexName “ DATAA“ (nameDhnensionStructure i) (nameDimension (port D A T U (inputPort) (nameInfornation (primaryN
23、ame “DATM2“ (nameStructure (cornplexName “DATAA“ (nameDimension 5-11 Copyright Government Electronics ! (outputport) (nameInformation (primaryName “RESUL“ (nameStructure (CornplexName “RESULT (nameDimension (nameDimensionStructe 2) (port RESULT3 (outputport) (nameInformation (primaryName “RESULT3“ (
24、namestructure (CornplexName “RESULT (nameDimension (nameDimensionStructe 3) (portBundle RESULT (portList (portRef REsULT3) (portRef RESLT2) (portRef RESULT1) (portRef RESULTO) (primaryName “RESULT 3 :O“ (nameInformation (nameStructure (cornplexName “RESULT“ (nameDimension (nameDimensionStructure (se
25、quence 3 0 ) ) ) ) ) ) ) ) ) (clusterHeader (property LPM-TYPE (stnng “LPM-ADD-SUB“) (property LPM-Width (integer 4) (cell fibex (cellHeader 5-13 Copyright Government Electronics ! (signaiJoined (portnstanceRef 42 (instanceRef I 2 ) ) (portInstanceRef DATAA2 (instanceRef 13) (signai PRESENT3 (signal
26、Joined (portInstanceRef Q3 (instanceRef E) (portInstanceRef DATAA3 (instanceRef 13) (signalGroup PRESENT (signalLis t (signaiRef PRESENTO) (signaiRef PRESENTI) (signaiRef PRESENT2) (signalRef PRESENT3) (signai RESL (signdoined (portInstanceRef DATA0 (instanceRef Il) (portInstanceRef RESULTO (instanc
27、eRef 13) (portRef RESULTO) (signai RESULT1 (signdoined (portInstanceRef DATA1 (instanceRef Il) (portInstanceRef RESULT1 (instanceRef 13) (portRef RESLTl) (signai RESULT2 (signdoined (pordstanceRef DATA2 (instanceRef Il) (portInstanceRef RESULT2 (instanceRef 13) (portRef RESLT2) (signai RESULT3 (sign
28、doined (portInstanceRef DATA3 (instanceRef Il) (portInstanceRef RESULT3 (instanceRef 13) (portRef RESLB) (SignalGroup RESULT (signaiList (signaiRef RESL) (signaiRef RESULTI) (signalRef R.E.SUL-2) (signaRef RESLT3) (connectivity structure) (design fibex (cellRef fibex (designHeader (IibraryRef fibex)
29、 (designunits) 5-16 Copyright Government Electronics LPM-WIDTHB : positive; LPM-WIDTHS : positive; LPM-WIDTH : positive; LPM-REPRESENTATION : string := UNSIGNED; LPM-PIPELINE : integer := O; LPM-TYPE: string := L-MULT; LPMHINT : string := UNUSED); port ATM : in std-logic-vector(LPM-WlDTHA-1 downto O
30、); DATAB : in std-logic-vector(LPM_WIDTHB-l downto O); SUM: in std-logic_vector(LPM_wIDTHS-l downto O) := (OTHERS = O7); RESULT : out std-logic-vector(LPM_WIDI3IP-l downto O); end component; 6.2 COMPONENT INSTANTIATION .62.1 Port All the used port connections are defined in port map construct of VHD
31、L. The unused optional ports were left out from the port map and its default value from the component declaration will be used. For example, the u1 instance in this example only use aset optional port of LPM-FF so other unused optional ports were left our from the port map statement. ul: lpm-ff PORT
32、 MAP (data = result, clock =Clock, clear = aset, q = last); 6-1 Copyright Government Electronics u2: lpm-ff GENERIC MAP (LPM-WIDTH = 4, LPM-AVALUE = 1) PORT MAP (data = last, clock =clock, clear = aset, q = present); u3: lpmadd-sub GENERIC MAP (LPM-WIDTH = 4) PORT MAP (dataa = present, datab = last,
33、 sum = result); END Ipm; 6-3 Copyright Government Electronics parameter lpm-type = “lpm-mult“ ; parameter lpm-widtha = 1 ; parameter lpm-widthb = 1 ; parameter lpm-widths = 1 ; parameter lpm-widthp = 1 ; parameter lpm-pipeline = O ; parameter lpm-representation = “UNSIGNED“ ; input clock ; input acl
34、r ; input lpm-widtha-l:O dataa ; input lpm-widthb-1 :O datab ; input lpm-widths-l:O sum ; output lpm-widthp-1 :O result; module body . . . endmodule; 7.2 MODULE INSTANTIATION 72.1 P o r t To avoid the potential mismatch pin connection, LPM required port connection by name. Ail used port connections
35、needed to be defined in port connect from the instantiation. And the unused optional ports were left out from the port connection and its default value from the module declaration will be used. For example, the u1 instance in this example only use aset optional port of LPM-FF so other unused optiona
36、l ports were left our from the port conncetion statement. LPM-FF u1 (.data(result), .q(last), .clock(clock), .aset(clear); 7- 1 Copyright Government Electronics defparam u 1 .Ipm-avalue = 1 ; Datai3 3:0 Result 3:0 - 7.3 EXAMPLE 73.1 Schematic description UM-Width = 4 LPM-Avalue = 1 LPM-Width = 4 LPM
37、-Avaiue = 1 The schematic example is shown in the following figure. LPM-TYPE = UM-ADD-SUB WM-Width = 4 CLEAR 73.2 Verilog description / Description: LPM instantiation / include “/lpm_comp.v” module fibex (clock, clear, result); input clear; input clock; . inout 3:0 result; wire 3:0) last; wire 3:0 p
38、resent; 7-2 Copyright Government Electronics defparam u1 .lprn-width = 4; defparam u 1 .lpm-avalue = 1 ; LPM-FF u2 (.data(last), .q(present), .clock(clock), .aset(clear); defparam u2.lpm-width = 4; defparam u2.lpm-avalue = 1; LPM-ADDSUB u3 (. dataa(present), .datab( las t), .result( result); defpara
39、m u3.lpm-width = 4; endmodule 7-3 Copyright Government Electronics use lEEE.std-iogic-ll64.al; 8- 1 Copyright Government Electronics constant UNSIGNED : string := “UNSIGNED“; constant ADD : string := “ADD“; constant SUB : string := “SUB“; constant U p : string := “UP“; constant DOWN : string := “DOW
40、N“; constant LOGICAL : string := “LOGICAL“; constant ROTATE : string := “ROTATE“; constant ARITHMETIC : string := “ARITHMETIC“; constant REGISTERED : sxing := “REGISTERED“; constant UNREGISTERED : string := “UNREGISTERED“; constant F : string := “F“; constant FD : string := “FD“; constant FR : strin
41、g := “FR“; constant FDR : string := FDR“; constant UNUSED : string := “UNUSED“; constant FFTYPE-DFF : string := “DFF“; constant FFIYPE-TFF : string := “TFF“; constant L-CONSTANT : string := “LPM-CONSTA“; constant L-INV : string := “LPM-INV“; constant L-AND : string := “LPM-AND“; constant L-OR : siri
42、ng := “LPM-OR; constant L-XOR : sing := “LPM-XOR“; constant L-BUSTRT : string := “LPM-BUSTRI“; constant L-MUX : string := “LPM-MUX“; constant L-DECODE : string := “LPM-DECODE; constant L-CMHIFT : string := “LPM-CLSHIFT“; constant L-ADDSUB : string := “LPM-ADD-SUB“; constant L-COMPARE : string := “LP
43、M-COMPARE“; constant L-MULT : string := “LPM-MTJLT“; constant L-ABS : string := “LPM-ABS“; constant L-COUNTER : string := “LPM-COUNTER“; constant L-LATCH : string := “UM-LATCH“; constant L-FF : string := “LPM_FF“; constant L-S“REG : string := “LPM-SHIFTREG“; constant L-TFF : string := “LPM-TF“; cons
44、tant L-W-DQ : string := *LPM_RAM_DQ“; constant L-FL4h-IO : string := “LPM-FMM-IO“; constant L-ROM : string := “LPM-ROM“; constant L-ITABLE : string := “LPM-TTABLE; constant L-FSM : string := “LPM-FSM; constant L-INPAD : string := “LPM_INPAD“; constant L-OUPAD : string := “LPM-OTPAD“; constant L-BPAD
45、 : string := “LPM-BIPAD“; type STD-LOGIC-2D is array (NATURAL RANGE o, NATURAL RANGE o) of STD-LOGIC; Copyright Government Electronics LPM-MODULUS: string := UNUSED; LPM-AVALUE : string := UNUSED; LPM-SVALUE : string := UNUSED; LPM-DIRECTION : string := UNUSED; LPM-TYPE: string := L-COUNTER; LPM-PVA
46、LUE : string := UNUSED; LPM-”T : string := UNUSED); port (DATA: in std-logic-vector(LPM-WIDm-1 downto O):= (OTHERS = O); CLOCK : in std-logic ; CLK-EN : in std-logic := I; CNT-EN : in std-logic := 1; UPDOWN : in std-logic := 1; SLOAD : i n std-logic := O; SSET : in std-logic := O; SCLR : in std-logi
47、c := O; ALOAD : in std-logic := O; ASET : in std-logic := O; ACLR : in std-logic := O; EQ : out std-logic; Q : out std-logic-vector(LPM-WDW- 1 downto O); . end component; component LPM-m S generic (LPM-WIDTH : positive; port (DATA : in std-logic-vector(LPM-Wm- 1 downto O); LPM-TYPE: string := L-ABS)
48、; RESULT : out std-logic-vector(LPM-WIDm-1 downto O); OVERFLOW: out std-logic); end component; component LPM-MULT generic (LFM-WIDTHA : positive; LPM-WIDTHB : positive; LPM-WIDTHS : positive; LPM-WIDTHP : positive; LPM-REPFESENTATION : String := UNSIGNED; LPM-PIPELINE : integer := O; LPM-TYPE: strin
49、g := L-MULT; LPM-HINT : string := UNUSED); port (DATAA : in std-logic-vector(LPM-WIDM_WIDTHA-l downto O); DATAB : in std-logic-vector(LPM-WID=-1 downto O); ACLR : in std-logic := O; CLOCK : in std-logic := O; SUM: in std-logic-vector(LPM-WIDTHS-1 downto O) := (OTHERS = O); RESULT : out std-logic-vector(LPM-WrDm- 1 downto O); end component;