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1、 Rev 1.31 2011/11/18 AM8EB151A DATA SHEET 佑佑佑佑佑佑佑佑華華華華華華華華微微微微微微微微電電電電電電電電子子子子子子子子股股股股股股股股份份份份份份份份有有有有有有有有限限限限限限限限公公公公公公公公司司司司司司司司 A Al lp ph ha a MMi ic cr ro oe el le ec ct tr ro on ni ic cs s C Co or rp p. . 新竹市光復路二段295號9樓之1 9F-1, 295, Sec. 2, Kuang Fu Rd., Hsinchu, Taiwan 電話：03-573 6660 Tel : +8
2、86-3-573 6660 傳真：03-573 6661 Fax: +886-3-573 6661 .tw .tw Alpha Microelectronics Corp. AM8EB151A Rev 1.31 2011/11/18 2 Revision History Rev Date Description Page 1.00 2008/12/18 New Release. - 1.10 2009/4/10 1) Modify Section 1.1: Features. 2) Modify Chapter 4: Instruction Set. 3) Modify Section 5.2
3、: DC Characteristics (TOP = 25C). - 1.20 2011/6/21 Modify Chapter 7: Ordering Information. - 1.30 2011/9/26 1) Modify Section 1.3: Pin Assignment. 2) Modify Chapter 6: Package Dimension. 3) Modify Chapter 7: Ordering Information. - 1.31 2011/11/18 Modify Section 5.2: DC Characteristics (TOP = 25C).
4、43 AM8EB151A Rev 1.31 2011/11/18 3 Table of Contents 1. General Description.5 1.1 Features 5 1.2 Block Diagram .7 1.3 Pin Assignment8 1.4 Pin Description.9 2. Memory Organization 10 2.1 Program Memory.10 2.2 Data Memory.11 3. Function Description .11 3.1 General Function Register.11 3.2 I/O Control
5、Register (Addressed by IOST, IOSTR Instruction)15 3.3 Special Function Register (Addressed by SFUN, SFUNR Instruction)18 3.4 RESET.19 3.5 I/O Ports.21 3.6 Real Time Clock (Timer0) and Watchdog Timer (WDT)23 3.6.1 Timer0 23 3.6.2 Watchdog Timer (WDT). 23 3.6.3 Prescaler 23 3.6.4 Switching Prescaler A
6、ssignment 23 3.7 Oscillator Configuration24 3.7.1 IRC Mode. 25 3.7.2 EXT-R Mode. 25 3.7.3 LF-XTAL, XTAL, HF-XTAL Mode . 26 3.7.4 ERC Mode . 27 3.8 Interrupts28 3.8.1 External INT Interrupt. 28 3.8.2 Timer0 Interrupt . 28 3.8.3 PortB Input Change Interrupt. 28 3.8.4 Watchdog Timer Time-Out Interrupt
7、29 3.9 Power-Down (SLEEP) Mode29 3.10 Configuration Word30 4. Instruction Set31 5. Electrical Characteristics 43 5.1 Absolute Maximum Rating.43 5.2 DC Characteristics (Top = 25C)43 5.3 Temperature Characteristics (Range: -40C 100C)47 AM8EB151A Rev 1.31 2011/11/18 4 5.4 Voltage Characteristics (Tempe
8、rature = 25C) .50 6. Package Dimension.51 6.1 8-Pin PDIP 300 mil.51 6.2 8-Pin SOP 150 mil .52 6.3 10-Pin SSOP 150 mil.53 6.4 14-Pin PDIP 300 mil.54 6.5 14-Pin SOP 150 mil .55 7. Ordering Information .56 AM8EB151A Rev 1.31 2011/11/18 5 1. General Description AM8EB151A is a family of low cost, high sp
9、eed, high noise immunity and EPROM-embedded 8-bit CMOS micro-controllers. It employs RISC architecture with only 55 instructions. All instructions are executed in a single cycle except for program branches that take two cycles. AM8EB151A provides easy, but powerful and useful instruction sets that c
10、an directly or indirectly address its register files and data memory. 1.1 Features ? Wide operating voltage range: - Four oscillator periods: 2.0 5.5 V at 32 KHz, 2.2 5.5 V at DC-8 MHz, 2.6 5.5 V at DC-20 MHz. - Two oscillator periods: 2.0 5.5 V at 32 KHz, 2.2 5.5V at DC-8 MHz. 10 MHz 16 MHz and 20
11、MHz are not available. ? Wide operating frequency range: 32 KHz 20 MHz. ? Wide operating temperature range: 0C 70C. ? ROM: 1K x 14 bits. ? RAM: 48 x 8 bits. ? Selectable oscillator options: - IRC: Internal Resistor and Capacitor Oscillator. - EXT-R: External Resistor and Internal Capacitor Oscillato
12、r. - ERC: External Resistor and Capacitor Oscillator. - LF-XTAL: Low Frequency Crystal Oscillator. - XTAL: Crystal / Resonator Oscillator. - HF-XTAL: High Frequency Crystal / Resonator Oscillator. ? 6-level deep hardware stack. ? A total of 55 single-word instructions. ? All single-cycle instruction
13、s except for program branches, which are two-cycle. ? Direct, indirect addressing modes for data accessing. ? LGOTO and LCALL instructions allow access to any address in the ROM space. ? 8-bit real time clock / counter (Timer0) with 8-bit programmable prescaler. ? On-chip Watchdog Timer (WDT) with i
14、nternal oscillator for reliable operation and Watchdog Timer enable / disable control through software. ? Internal Power-On Reset (POR). ? Built-in Low Voltage Reset (LVR). ? Power-Up Reset Timer (PWRT) and Oscillator Start-Up Timer (OST). ? SLEEP function to reduce power consumption. AM8EB151A Rev
15、1.31 2011/11/18 6 ? I/O port PB with independent direction control. ? I/O pull-high, pull-down or open-drain setting through software control. ? One IR carrier output (38 KHz / 57 KHz). ? Four Interrupt sources: - Timer0 overflow - PB input change - External Interrupt Pin - Watchdog Timer Time-Out I
16、nterrupt (Available when enabled by programming Configuration Word.) ? Wake-up from SLEEP by: - External INT pin - PB input change - WDT Time-Out Interrupt or Reset ? Programmable Code Protection. AM8EB151A Rev 1.31 2011/11/18 7 1.2 Block Diagram Oscillator / Timing Control FSR Interrupt Control 6-L
17、evel Stack Program Counter EPROM / ROM Instruction Decoder Watchdog Timer SRAM IR Internal RC Control Software Interrupt Vector is at 001h and Global Hardware Interrupt Vector is at 008h. AM8EB151A supports LCALL and LGOTO instructions to access to any address in the ROM space. FIGURE 2.1 Program Me
18、mory Map and STACK STACK Level 6 Global H/W Interrupt Vector Reset Vector S/W Interrupt Vector STACK Level 1 STACK Level 2 STACK Level 3 STACK Level 4 STACK Level 5 PC 9 : 0 3FFh 008h 000h 001h . . . . . . . . . . . . . . . . AM8EB151A Rev 1.31 2011/11/18 11 2.2 Data Memory Data memory includes Gene
19、ral Function Registers and General Storage Registers. Data Memory is accessed either directly or indirectly through the FSR register. TABLE 2.1 File Map of Registers for AM8EB151A Address Description 00h Indirect Addressing Register 01h Timer0 02h PCL 03h STATUS 04h FSR 06h PortB 0Fh Interrupt Statu
20、s Register 10h 3Fh General Storage Register 3. Function Description 3.1 General Function Register ? INAR (Indirect Address Register): R0 R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction accessing this register can access data pointed by FSR (
21、R4). ? Timer0 (8-bit Real-Time Clock / Timer): R1 This register increases with an external signal edge applied to RTCC pin, or with an internal instruction cycle. It can be read or written as any other register. ? PCL (Low Byte of Program Counter): R2 This register increases itself in every instruct
22、ion cycle, except the condition shown as the figure below. Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 LCALL, CALLA, RET, RETIE, RETIA A9 A0 LCALL, LGOTO: From instruction word GOTOA: From the content of TBHP, ACC AM8EB151A Rev 1.31 2011/11/18 12 Status Register In terms of Program Counter, the
23、data of A9 are loaded from Bit 5 of Status Register, while A8 is always cleared. The configuration is shown as below: ? STATUS (Status Register): R3 The contents of R3 are listed in TABLE 3.1. TABLE 3.1 STATUS Register Bit Symbol Description 0 C Carry / Borrow Flag Bit C = 1, an ADD with carry occur
24、s, or a SUB without borrow occurs. C = 0, an ADD without carry occurs, or a SUB with borrow occurs. 1 DC Half Carry / Half Borrow Flag Bit DC = 1, an ADD with carry to the 4th low order bit occurs, or a SUB without borrow from the 4th low order bit occurs. DC = 0, an ADD without carry to the 4th low
25、 order bit occurs, or a SUB with borrow from the 4th low order bit occurs. 2 Z Zero Flag Bit Z = 1, the result of a logic operation is zero. Z = 0, the result of a logic operation is not zero. 3 PD Power Down Flag Bit After power-up or after executing CLRWDT instruction, PD = 1. After wake-up from S
26、LEEP instruction via Reset, Interrupt or WDT, PD = 0. 4 TO Time Overflow Flag Bit After power-up or after executing CLRWDT or SLEEP instruction, TO = 1. After a WDT time-out occurs when WDT reset is enabled, TO = 0. 5 PA0 Program Page Pre-Select Bit PA0 = 0, Program Page 0 ( 000h 1FFh ). PA0 = 1, Pr
27、ogram Page 1 ( 200h 3FFh ). 6 - General-purpose R/W bit. 7 RST RST = 1, wake up from Sleep Mode via PortB input change interrupt. A9 A8 PCL : A7 A0 Bit 5 Program Counter Instruction Word “ 0 ” AM8EB151A Rev 1.31 2011/11/18 13 ? FSR (File Select Register): R4 FSR is used as a pointer. Of which, Bit 0
28、 5 are used to select up to 64 registers (address: 00h 3Fh) in the indirect addressing mode while Bit 6 7 are not used and always read as 1, as shown in the following figure: 1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h INAR 01h Timer0 02h PCL 03h STATUS 04h FSR 06h PortB 0Fh Interrupt Status Registe
29、r 10h 3Fh SRAM ? PORTB: R6 PB7 : PB0, bi-directional I/O registers. ? Interrupt Status Register: RF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTIF EXIF PBIF T0IF * Bit 0 (T0IF): Timer0 overflow interrupt flag. Set as 1 when Timer0 overflows, reset by software. * Bit 1 (PBIF): PortB input chan
30、ge interrupt flag. Set as 1 when PortB input changes, reset by software. * Bit 2 (EXIF): External INT pin interrupt flag. Set as 1 when External INT pin interrupts, reset by software. * Bit 3 5: Not used. * Bit 6 (WDTIF): Watchdog time-out interrupt flag. Set as 1 when Watchdog time-out interrupts,
31、reset by software. * Bit 7: Not used. Interrupt Status Register (RF) is used only for interrupt procedures. The bit of RF will be set in line with the corresponding bit of FF register. That is to say, when the bit of FF register is cleared, the bit of RF register is read as 0. ? R10 R3F R10 R3F are
32、general storage registers. Location Selection for Indirect Addressing Mode AM8EB151A Rev 1.31 2011/11/18 14 ? T0MODE Register T0MODE is a readable / writable register, the contents of which are listed in the following Table. Bit Symbol Description Bit Value Timer Rate WDT Reset Rate WDT INT Rate 2 -
33、 0 PS2:PS0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 3 PSC Prescaler assign bit = 0, assigned to Timer0. = 1, assigned to WDT. 4 TE
34、 Timer0 source edge select bit = 0, TIM0 increments when low-to-high transition occurs on RTCC pin. = 1, TIM0 increments when high-to-low transition occurs on RTCC pin. 5 TS Timer0 signal source select bit = 0, from an internal instruction cycle clock. = 1, from a transition on RTCC pin. 6 INTF Inte
35、rrupt enable flag (Read Only) = 0, masked by DISI or hardware interrupt. = 1, enabled by ENI / RETIE instructions. 7 INTEDG Interrupt edge select bit = 0, interrupt on falling edge of INT pin. = 1, interrupt on rising edge of INT pin. Note: The first WDT Interrupt is 1/2 period after executing Reset
36、 function or CLRWDT instruction when Prescaler is assigned to WDT. AM8EB151A Rev 1.31 2011/11/18 15 3.2 I/O Control Register (Addressed by IOST, IOSTR Instruction) ? PortB I/O Mode Control Register: F6 (PortB) This register is both readable and writable. = 0, the relative I/O pin is in output mode.
37、= 1, the relative I/O pin is in input mode. ? PortB Input Change Interrupt Control Register: F9 This register is both readable and writable. * Bit 0 (PBEI0): = 0, disable the input change interrupt function of PB0 pin. = 1, enable the input change interrupt function of PB0 pin. * Bit 1 (PBEI1): = 0,
38、 disable the input change interrupt function of PB1 pin. = 1, enable the input change interrupt function of PB1 pin. * Bit 2 (PBEI2): = 0, disable the input change interrupt function of PB2 pin. = 1, enable the input change interrupt function of PB2 pin. * Bit 3 (PBEI3): = 0, disable the input chang
39、e interrupt function of PB3 pin. = 1, enable the input change interrupt function of PB3 pin. * Bit 4 (PBEI4): = 0, disable the input change interrupt function of PB4 pin. = 1, enable the input change interrupt function of PB4 pin. * Bit 5 (PBEI5): = 0, disable the input change interrupt function of
40、PB5 pin. = 1, enable the input change interrupt function of PB5 pin. * Bit 6 (PBEI6): = 0, disable the input change interrupt function of PB6 pin. = 1, enable the input change interrupt function of PB6 pin. * Bit 7 (PBEI7): = 0, disable the input change interrupt function of PB7 pin. = 1, enable the
41、 input change interrupt function of PB7 pin. ? Timer0 and WDT Prescaler Counter Register: FA This register is readable. The content of FA is the value of Prescaler Counter. ? Pull Down Control Register: FB This register is both readable and writable. * Bit 0 (PDB4): = 0, enable the internal pull-dow
42、n of PB4 pin. = 1, disable the internal pull-down of PB4 pin. * Bit 1 (PDB5): = 0, enable the internal pull-down of PB5 pin. = 1, disable the internal pull-down of PB5 pin. * Bit 2 (PDB6): = 0, enable the internal pull-down of PB6 pin. = 1, disable the internal pull-down of PB6 pin. * Bit 3 (PDB7):
43、= 0, enable the internal pull-down of PB7 pin. = 1, disable the internal pull-down of PB7 pin. AM8EB151A Rev 1.31 2011/11/18 16 * Bit 4 (PDB0): = 0, enable the internal pull-down of PB0 pin. = 1, disable the internal pull-down of PB0 pin. * Bit 5 (PDB1): = 0, enable the internal pull-down of PB1 pin
44、. = 1, disable the internal pull-down of PB1 pin. * Bit 6 (PDB2): = 0, enable the internal pull-down of PB2 pin. = 1, disable the internal pull-down of PB2 pin. * Bit 7 (PDB3): = 0, enable the internal pull-down of PB3 pin. = 1, disable the internal pull-down of PB3 pin. ? Open Drain Control Registe
45、r: FC This register is both readable and writable. * Bit 0 (ODB0): = 0, disable the internal open-drain of PB0 pin. = 1, enable the internal open-drain of PB0 pin. * Bit 1 (ODB1): = 0, disable the internal open-drain of PB1 pin. = 1, enable the internal open-drain of PB1 pin. * Bit 2 (ODB2): = 0, di
46、sable the internal open-drain of PB2 pin. = 1, enable the internal open-drain of PB2 pin. * Bit 3: General register read / write bit. * Bit 4 (ODB4): = 0, disable the internal open-drain of PB4 pin. = 1, enable the internal open-drain of PB4 pin. * Bit 5 (ODB5): = 0, disable the internal open-drain
47、of PB5 pin. = 1, enable the internal open-drain of PB5 pin. * Bit 6 (ODB6): = 0, disable the internal open-drain of PB6 pin. = 1, enable the internal open-drain of PB6 pin. * Bit 7 (ODB7): = 0, disable the internal open-drain of PB7 pin. = 1, enable the internal open-drain of PB7 pin. ? Pull High Co
48、ntrol Register: FD This register is both readable and writable. * Bit 0 (PHB0): = 0, enable the internal pull-high of PB0 pin. = 1, disable the internal pull-high of PB0 pin. * Bit 1 (PHB1): = 0, enable the internal pull-high of PB1 pin. = 1, disable the internal pull-high of PB1 pin. * Bit 2 (PHB2)
49、: = 0, enable the internal pull-high of PB2 pin. = 1, disable the internal pull-high of PB2 pin. * Bit 3: General register read / write bit. * Bit 4 (PHB4): = 0, enable the internal pull-high of PB4 pin. = 1, disable the internal pull-high of PB4 pin. AM8EB151A Rev 1.31 2011/11/18 17 * Bit 5 (PHB5): = 0, enable the internal pull-high of PB5 pin. = 1, disable the internal pull-high of PB5 pin. * Bit 6 (PHB6): = 0, enable the internal pull-high of PB6 pin. = 1,