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1、IS61LV51216ISSI512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLYMARCH 2005FEATURES High-speed access time: 8, 10, and 12 ns CMOS low power operation Low stand-by power: Less than 5 m A (typ.) CMOS stand-by TTL compatible interface levels Single 3.3V power supplyDESCRIPTIONThe ISSI I
2、S61LV51216 is a high-speed, 8M-bit static RAM organized as 525,288 words by 16 bits. It is fabricated using ISSIs high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.When CE is HIG
3、H (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytesEasy memory expansion is provided by using Chip Enable and Outpu
4、t Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.Industrial temperature availableLead-free availableThe IS61LV51216 is packaged in the JEDEC standard44-pin TSOP Type II and 48-p
5、in Mini BGA (9mm x 11mm).FUNCTIONAL BLOCK DIAGRAMA0-A18DECODER512K x 16MEMORY ARRAYVDDGNDI/O0-I/O7I/OLower ByteCOLUMN I/ODATAI/O8-I/O15CIRCUITUpper ByteCEOECONTROLWECIRCUITUBLBCopyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci
6、fication and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
7、 and before placing orders for products.Integrated Silicon Solution, Inc. 1-800-379-47741Rev. B03/10/05IS61LV51216ISSITRUTH TABLEI/O PINModeWECEOELBUBI/O0-I/O7I/O8-I/O15VDD CurrentNot SelectedXHXXXHigh-ZHigh-ZISB1, ISB2Output DisabledHLHXXHigh-ZHigh-ZICCXLXHHHigh-ZHigh-ZReadHLLLHDOUTHigh-ZICCHLLHLH
8、igh-ZDOUTHLLLLDOUTDOUTWriteLLXLHDINHigh-ZICCLLXHLHigh-ZDINLLXLLDINDINPIN CONFIGURATIONS44-Pin TSOP (Type II)44A17A01A1243A16A2342A15A3441OEA4540UB639CELBI/O0738I/O15I/O1837I/O14I/O2936I/O13I/O31035I/O12VDD1134GNDGND1233VDDI/O41332I/O11I/O51431I/O10I/O61530I/O9I/O71629I/O81728A18WEA51827A14A61926A13A
9、72025A12A82124A11A92223A10PIN DESCRIPTIONSA0-A18Address InputsI/O0-I/O15Data Inputs/OutputsCEChip Enable InputOEOutput Enable InputWEWrite Enable InputLBLower-byte Control (I/O0-I/O7)UBUpper-byte Control (I/O8-I/O15)NCNo ConnectionVDDPowerGNDGround2Integrated Silicon Solution, Inc. 1-800-379-4774Re
10、v. B03/10/05IS61LV51216ISSI PIN CONFIGURATIONS48-Pin mini BGA (9mmx11mm)123456ALBOEA0A1A2N/CBI/O8UBA3A4CEI/O0CI/O9I/O10A5A6I/O1I/O2DGNDI/O11A17A7I/O3VDDEVDDI/O12GNDA16I/O4GNDFI/O14I/O13A14A15I/O5I/O6GI/O15NCA12A13WEI/O7HA18A8A9A10A11NCPIN DESCRIPTIONSA0-A18Address InputsI/O0-I/O15Data Inputs/Outputs
11、CEChip Enable InputOEOutput Enable InputWEWrite Enable InputLBLower-byte Control (I/O0-I/O7)UBUpper-byte Control (I/O8-I/O15)NCNo ConnectionVDDPowerGNDGround1234567ABSOLUTE MAXIMUM RATINGS(1)SymbolParameterValueUnitVTERMTerminal Voltage with Respect to GND0.5 to VDD+0.5VVDDVDD Related to GND0.3 to +
12、4.0VTSTGStorage Temperature65 to +150CPTPower Dissipation1.0WNote:1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
13、 the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.89101112Integrated Silicon Solution, Inc. 1-800-379-47743Rev. B03/10/05IS61LV51216ISSIOPERATING RANGERangeAmbient TemperatureVDDCommercial0C to
14、+70C3.3V +10%, -5%Industrial40C to +85C3.3V +10%, -5%DC ELECTRICAL CHARACTERISTICS (Over Operating Range)SymbolParameterTest ConditionsMin.Max.UnitVOHOutput HIGH VoltageVDD = Min., IOH = 4.0 mA2.4VVOLOutput LOW VoltageVDD = Min., IOL = 8.0 mA0.4VVIHInput HIGH Voltage2.2VDD + 0.3VVILInput LOW Voltage
15、(1)0.30.8VILIInput LeakageGND VIN VDDCom.11AInd.55ILOOutput LeakageGND VOUT VDDCom.11AOutputs DisabledInd.55Notes:1. VIL (min.) = 2.0V for pulse width less than 10 ns.POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)-8-10-12SymbolParameterTest ConditionsMin.Max.Min.Max.Min. Max.UnitICCVDD Dynam
16、ic OperatingVDD = Max.,Com.11010090mASupply CurrentIOUT = 0 mA, f = fMAXInd.120110100ISB1TTL Standby CurrentVDD = Max.,Com.303030mA(TTL Inputs)VIN = VIH or VILInd.353535CE VIH, f = 0ISB2CMOS StandbyVDD = Max.,Com.202020mACurrent (CMOS Inputs)CE VDD 0.2V,Ind.252525VIN VDD 0.2V, orVIN 0.2V, f = 0Note:
17、1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.4Integrated Silicon Solution, Inc. 1-800-379-4774Rev. B03/10/05IS61LV51216ISSICAPACITANCE(1)1SymbolParameterConditionsMax.UnitCINInput CapacitanceVIN = 0V6pFCOUTInput/Output CapacitanceVO
18、UT = 0V8pF2Note:1. Tested initially and after any design or process changes that may affect these parameters.3AC TEST CONDITIONS4ParameterUnitInput Pulse Level0V to 3.0V5Input Rise and Fall Times3 nsInput and Output Timing1.5Vand Reference LevelOutput LoadSee Figures 1 and 26AC TEST LOADS7319 8ZO =
19、50503.3VOUTPUT1.5VOUTPUT30 pF9Includingjig and5 pFscope353 Includingjig and10scope11Figure 1Figure 212Integrated Silicon Solution, Inc. 1-800-379-47745Rev. B03/10/05IS61LV51216ISSIREAD CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)-8-10-12SymbolParameterMin.Max.Min.Max.Min.Max.UnittRCRea
20、d Cycle Time81012nstAAAddress Access Time81012nstOHAOutput Hold Time333nstACECE Access Time81012nstDOEOE Access Time3.545nstHZOE(2)OE to High-Z Output3405nstLZOE(2)OE to Low-Z Output000nstHZCE(2CE to High-Z Output030406nstLZCE(2)CE to Low-Z Output333nstBALB, UB Access Time3.545nstHZB(2)LB, UB to Hig
21、h-Z Output030304nstLZB(2)LB, UB to Low-Z Output000nstPUPower Up Time000nstPDPower Down Time81012nsNotes:1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1.2. Tested with the loa
22、d in Figure 2. Transition is measured 500 mV from steady-state voltage.AC WAVEFORMSREAD CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)t RCADDRESSt AAt OHAt OHA DOUTPREVIOUS DATA VALIDDATA VALIDREAD1.eps6Integrated Silicon Solution, Inc. 1-800-379-4774Rev. B03/10/05IS61LV51216ISSIREAD CYCLE NO. 2(1,3)ADDRESStRCtAAtOHAOE