dsp实验报告.docx

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1、dsp实验报告DSP课程设计CCS音视频实验报告2021级电科（2）班陈涛2021329600102刘敏2021329600109徐有德2021329600116目录一、功能 (3)二、硬件原理 (3)1、接口 (3)2、外设 (3)三、软件实现 (3)1、寄存器配置 (3)2、流程图 (4)四、实验代码： (8)五、实验截图 (23)一、功能实现从摄像头的音视频音视频输入，经过dsp开发板处理之后在显示屏上一起同步显示输出，可在现实中实现远程电子监视以及视频会议等功能。达到稳定的输出视屏与稳定的输出音频，达到输出时的一致性，保证输出与记录的相一致。二、硬件原理1、接口实验选用的硬件平台为SE

2、ED-DVS6446 开发板。SEED-DVS6446采用TMS320DM6446 处理器，用于满足下一代嵌入式系统的网络多媒体的编解码处理应用。该开发板采用双核架构ARM+DSP，其中ARM 处理器采用ARM926EJ-S核，工作主频为297MHz，DSP 处理器采用TI 的高端DSP 核C64x+，工作主频为594MHz。SEED-DVS6446 开发板外设主要包括：双路视频采集，支持CVBS和VGA 输出；立体声音频输入输出接口；RS232 标准异步通信串口，用于控制台控制；硬盘接口，方便本地数据存储，实现数字视频录像机功能；高速数据传输接口：10M/100M 以太网接口，实现数字视频服

3、务器功能。2、外设1 Digital ccd camera（摄像头）2显示屏3SEED XDS-510PLUS 仿真器三、软件实现1、寄存器配置为线性汇编指定寄存器C6000 只有 2 个交叉通路，这限制了在一个周期内 C6000 的一组的功能单元从另外一组的寄存器中取数的个数。编译器必须为每条指令选择组，称为分配。推荐在开始时不要手工分配线性汇编源代码，使编译器有更多自由分配和优化代码。如果编译器在软件流水循环中没有找到最优的分配方法，这时才需要手工分配指令，使用到的功能单元平均分配，从而达到最优。用户可以用.reg 伪指令或.rega, .regb 伪指令来选择寄存器。 .reg 伪指令使

4、用户能为每个值设置一个描述名，这些值需要存储在寄存器中。汇编优化器为选择一个寄存器，它与为操作这个值的指令选择的功能单元一致，即寄存器和功能单元同一组。寄存器可以用两条伪指令直接分配，.rega 和.regb。.rega 指令用于把符号限制在 A 组寄存器，.regb 指令用于把符号限制在 B 组寄存器。2、流程图初始化输入原始信号定义滤波器系数为原始信号和系数指定寄存器做滤波算法本次滤波结束待滤波系数减一是否有待滤波数据滤波结束四、验代码如下：1、Ddr实验：Main.c:#include stdio.h#include davincievm.h#include davincievm_emi

5、f.hextern Int16 ddr_test( );/* - * * * main( ) * * * * - */void main( void )if(ddr_test() != 0)printf( Testing DDR2 MEMORY FAIL. n);elseprintf( Testing DDR2 MEMORY PASS. n);Main_test.c:#include davincievm.hUint32 memfill32( Uint32 start, Uint32 len, Uint32 val )Uint32 i;Uint32 end = start + len;Uint

6、32 errorcount = 0;/* Write Pattern */for ( i = start; i *( volatile Uint32* )i = val;/* Read Pattern */for ( i = start; i if ( *( volatile Uint32* )i != val )errorcount+;printf(address %x is errorn ,start+i);break;return errorcount;Uint32 memaddr32( Uint32 start, Uint32 len )Uint32 i;Uint32 end = st

7、art + len;Uint32 errorcount = 0;/* Write Pattern */for ( i = start; i *( volatile Uint32* )i = i;/* Read Pattern */for ( i = start; i if ( *( volatile Uint32* )i != i )errorcount+;printf(address %x is errorn ,start+i);break;return errorcount;Uint32 meminvaddr32( Uint32 start, Uint32 len )Uint32 i;Ui

8、nt32 end = start + len;Uint32 errorcount = 0;/* Write Pattern */for ( i = start; i *( volatile Uint32* )i = i;/* Read Pattern */for ( i = start; i if ( *( volatile Uint32* )i != i )errorcount+;printf(address %x is errorn ,start+i);break;return errorcount;Ddr.c:#include davincievm.hextern memfill32(

9、Uint32 start, Uint32 len, Uint32 val );extern memaddr32( Uint32 start, Uint32 len );extern meminvaddr32( Uint32 start, Uint32 len );Uint32 ddr_test( )Uint32 retcode = 0;Uint32 ddr_base=0x80000000; / DDR memory space Uint32 ddr_size = 0x7000000; / 1 MBretcode |= memfill32( ddr_base, ddr_size, 0xFFFFF

10、FFF );retcode |= memfill32( ddr_base, ddr_size, 0xAAAAAAAA );retcode |= memfill32( ddr_base, ddr_size, 0x55555555 );retcode |= memfill32( ddr_base, ddr_size, 0x00000000 );retcode |= memaddr32( ddr_base, ddr_size );retcode |= meminvaddr32( ddr_base, ddr_size );return retcode;2、音视频实验：Main.c/* Copyrigh

11、t 2021 by Spectrum Digital Incorporated.* All rights reserved. Property of Spectrum Digital Incorporated.* Not for distribution.*/* AIC33 Tests*/#include stdio.h#include davincievm.hextern Int16 video_loopback_test();extern Int16 aic23_test( );/* -* * * main( ) * * * * - */void main( void )/* */DA V

12、INCIEVM_init( );DA VINCIEVM_GPIO_setDirection(41,0);DA VINCIEVM_GPIO_setOutput(41,1);DA VINCIEVM_GPIO_setDirection(39,0);DA VINCIEVM_GPIO_setOutput(39,1);video_loopback_test();aic23_test();ideo_test.c#include davincievm_i2c.h#define TVP5150_I2C_ADDR 0x5dUint16 temp;Uint32 temp1,temp25;/* - * * * tvp

13、5150_rset * * * * Set codec register regnum to value regval * * * - */void tvp5150_rset( Uint8 regnum, Uint8 regval )Uint8 cmd2;cmd0 = regnum; / 8-bit Register Addresscmd1 = regval; / 8-bit Register Datatemp=DA VINCIEVM_I2C_write( TVP5150_I2C_ADDR, cmd, 2);/* - * * * tvp5150_rget * * * * Return valu

14、e of codec register regnum * * * - */Uint8 tvp5150_rget( Uint8 regnum )Uint8 cmd2;cmd0 = regnum; / 8-bit Register Addresscmd1 = 0; / 8-bit Register DataDA VINCIEVM_I2C_write ( TVP5150_I2C_ADDR, cmd, 1 );DA VINCIEVM_I2C_read ( TVP5150_I2C_ADDR, cmd, 1 );return cmd0;/* - * * * tvp5150_init( ) * * * In

15、itialize the tvp5150 * * * - */void tvp5150_init( )DA VINCIEVM_waitusec( 1000 );tvp5150_rset( 0x00, 0x00 ); / Input Video: CVBS : VI_2_Btvp5150_rset( 0x03, 0x6d);tvp5150_rset( 0x09, 0x8B);tvp5150_rset( 0x0a, 0x80 );tvp5150_rset( 0x0b, 0x00 );tvp5150_rset( 0x0D, 0x07 ); / Enabling clock & Y/CB/CR inp

16、ut formattvp5150_rset( 0x0F, 0x02 );tvp5150_rset( 0x15, 0x05 );tvp5150_rset( 0x1B, 0x14 );DA VINCIEVM_waitusec( 1000 ); / wait 1 msec#define NTSC 1#if NTSC#define BASEP_X 0x7A / 122#define BASEP_Y 0x12 / 18#elif PAL#define BASEP_X 0x84 / 132#define BASEP_Y 0x16 / 22#endif/* - * * * vpfe_init( ) * *

17、* NTSC: * * Width: 720 * * Height: 480 * * * * * * - */void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height )VPFE_SYN_MODE = 0x00032F84; / interlaced, with VD pority as negativeVPFE_HD_VD_WID = 0;VPFE_PIX_LINES = 0x02CF0271;/* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec* for

18、BT.656 mode, this setting captures only the 720x480 of the* active NTSV video window*/VPFE_HORZ_INFO = width VPFE_HSIZE_OFF = width VPFE_VERT_START = 0; / Vertical start lineVPFE_VERT_LINES = height 1; / Vertical linesVPFE_CULLING = 0xFFFF00FF; / Disable cullng/* Interleave the two fields*/VPFE_SDOF

19、ST = 0x00000249;VPFE_SDR_ADDR = buffer;VPFE_CLAMP = 0;VPFE_DCSUB = 0;VPFE_COLPTN = 0xEE44EE44;VPFE_BLKCMP = 0;VPFE_FPC_ADDR = 0x86800000;VPFE_FPC = 0;VPFE_VDINT = 0;VPFE_ALAW = 0;VPFE_REC656IF = 0x00000003;/* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position*/VPFE_CCDCFG = 0x00000800;VPFE_FMTCFG

20、 = 0;VPFE_FMT_HORZ = 0x000002D0;VPFE_FMT_VERT = 0x00000272;VPFE_FMT_ADDR0 = 0;VPFE_FMT_ADDR1 = 0;VPFE_FMT_ADDR2 = 0;VPFE_FMT_ADDR3 = 0;VPFE_FMT_ADDR4 = 0;VPFE_FMT_ADDR5 = 0;VPFE_FMT_ADDR6 = 0;VPFE_FMT_ADDR7 = 0;VPFE_PRGEVEN_0 = 0;VPFE_PRGEVEN_1 = 0;VPFE_PRGODD_0 = 0;VPFE_PRGODD_1 = 0;VPFE_VP_OUT = 0

21、x04e22D00;VPFE_PCR = 0x00000001; / Enable CCDC/* - * * * vpbe_init( ) * * * NTSC: * * Width: 720 * Height: 480 * * * * * - */void vpbe_init( Uint32 buffer, Uint32 width, Uint32 height, Uint32 cb_enable )/* Setup VPBE*/VPSS_CLK_CTRL = 0x00000018; / Enable DAC and VENC clock, both at 27 MHz VPBE_PCR =

22、 0; / No clock div, clock enable/* Setup OSD*/OSD_MODE = 0x0000007f; / Blackground color blue using clut in ROM0 OSD_OSDWIN0MD = 0; / Disable both osd windows and cursor window OSD_OSDWIN1MD = 0;OSD_RECTCUR = 0;OSD_VIDWIN0OFST = width 4;OSD_VIDWIN0ADR = buffer;OSD_BASEPX = BASEP_X;OSD_BASEPY = BASEP

23、_Y;OSD_VIDWIN0XP = 0;OSD_VIDWIN0YP = 0;OSD_VIDWIN0XL = width;OSD_VIDWIN0YL = height 1;OSD_MISCCTL = 0;OSD_VIDWINMD = 0x00000003; / Disable vwindow 1 and enable vwindow 0/ Frame mode with no up-scaling /* Setup VENC*/VENC_VMOD = 0x00000043; / Standard NTSC interlaced outputVENC_VDPRO = cb_enable VENC

24、_DACTST = 0;VENC_DACSEL = 0x000213;/* - * * video_loopback_test( ) * * * * * * * - */Int16 video_loopback_test( )tvp5150_init( );vpfe_init( 0x81000000, 720, 576 ); / Setup Front-Endvpbe_init( 0x81000000, 720, 576, 0); / Setup Back-Endreturn 0;Aic23_test.c/* Copyright 2021 by Spectrum Digital Incorpo

25、rated.* All rights reserved. Property of Spectrum Digital Incorporated.* Not for distribution.*/* AIC23 Linein to Lineout loop Test for C64x+*/#include davincievm_aic33.hextern Int16 aic23_linein_to_lineout_loop_test( );Int16 aic23_test()Int16 retcode = 0;retcode |= aic23_linein_to_lineout_loop_test

26、( );return retcode;Aic23_lineout.c/* Copyright 2021 by Spectrum Digital Incorporated.* All rights reserved. Property of Spectrum Digital Incorporated.* Not for distribution.*/* AIC33 Lineout Tone Test for C64xx+*/#include davincievm_aic33.h/* - * * * AIC33 Lineout Tone * * * AIC33.MCLK = PLL1705.SCK

27、03 * * FS = ( AIC33.MCLK * K ) / ( 2048 * P ) * * * * * For a FS=44.1 kHz & MCLK=33.8688 MHz * : 44.1kHz = ( 33.8688 MHz * K ) / ( 2048 * P ) * : P = 2, KJ.D = 5.3333 * * * * * For a FS=48 kHz & MCLK=33.8688 MHz * : 48kHz = ( 33.8688 MHz * K ) / ( 2048 * P ) * : P = 2, KJ.D = 5.8049 * * * * * For a

28、FS=44.1 kHz & MCLK=22.5792 MHz * : 44.1kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) * : P = 2, KJ.D = 8.0000 * * * * * For a FS=48 kHz & MCLK=22.5792 MHz * : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) * : P = 2, KJ.D = 8.7075 * * - */Int16 aic23_lineout_tone_test( )Int16 msec;AIC33_CodecHandle aic33hand

29、le;AIC33_Config aic33config = 0x0000, / 0-0 Page Select 0xAA00, / 0-1 Software Reset 0x0000, / 0-2 Codec Sample Rate Select / For: FS=44.1 kHzMCLK=33.8688 MHz/0x0092, / 0-3 PLL Reg A /0x0014, / 0-4 PLL Reg B /0x0034, / 0-5 PLL Reg C /0x0014, / 0-6 PLL Reg D /0x008A, / 0-7 Codec Datapath Setup / For:

30、 FS=48 kHzMCLK=33.8688 MHz/0x0092, / 0-3 PLL Reg A /0x0014, / 0-4 PLL Reg B /0x007D, / 0-5 PLL Reg C /0x0004, / 0-6 PLL Reg D /0x000A, / 0-7 Codec Datapath Setup / For: FS=44.1 kHzMCLK=22.5792 MHz/0x0092, / 0-3 PLL Reg A /0x0020, / 0-4 PLL Reg B /0x0000, / 0-5 PLL Reg C /0x0000, / 0-6 PLL Reg D /0x0

31、08A, / 0-7 Codec Datapath Setup / For: FS=48 kHzMCLK=22.5792 MHz0x0092, / 0-3 PLL Reg A 0x0020, / 0-4 PLL Reg B 0x006E, / 0-5 PLL Reg C 0x0023, / 0-6 PLL Reg D 0x000A, / 0-7 Codec Datapath Setup 0x00C0, / 0-8 Audio Serial Data Reg A - BCLK=MasterWCLK=Master3DEffects=OFFDigitalMIC=OFF0x0000, / 0-9 Au

32、dio Serial Data Reg B 0x0000, / 0-10 Audio Serial Data Reg C 0xAA00, / 0-11 Overflow Status Reg 0x0000, / 0-12 Digital Filter Ctrl Reg 0x0000, / 0-13 Headset Detection Reg A 0x0000, / 0-14 Headset Detection Reg B 0x0000, / 0-15 Left ADC PGA Gain Ctrl Reg 0x0000, / 0-16 Right ADC PGA Gain Ctrl Reg 0x

33、00FF, / 0-17 MIC3L/R to Left ADC Ctrl Reg 0x00FF, / 0-18 MIC3L/R to Right ADC Ctrl Reg 0x0004, / 0-19 LINE1L to Left ADC Ctrl Reg 0x0078, / 0-21 LINE1R to Left ADC Ctrl Reg 0x0004, / 0-22 LINE1R to Right ADC Ctrl Reg 0x0078, / 0-24 LINE1L to Right ADC Ctrl Reg 0x0000, / 0-25 MICBIAS Control Reg 0x00

34、00, / 0-26 Left AGC Control Reg A 0x0000, / 0-27 Left AGC Control Reg B 0x0000, / 0-28 Left AGC Control Reg C 0x0000, / 0-29 Right AGC Control Reg A 0x0000, / 0-30 Right AGC Control Reg B 0x0000, / 0-31 Right AGC Control Reg C 0xAA00, / 0-32 Left AGC Gain Reg 0xAA00, / 0-33 Right AGC Gain Reg 0x0000

35、, / 0-34 Left AGC Noise Gate Debounce 0x0000, / 0-35 Right AGC Noise Gate Debounce 0xAA00, / 0-36 ADC Flag Reg 0x00E0, / 0-37 DAC Power & Output Dvr Ctrl Reg 0x0010, / 0-38 High Power Output Dvr Ctrl Reg -HPRCOM=SingleEndShortCircuit=OFF0xFFFF, / 0-39 Reserved 0x0000, / 0-40 Output Stage Ctrl Reg 0x

36、0000, / 0-41 DAC Output Switching Ctrl Reg 0x0000, / 0-42 Output Driver Pop Reduction Reg 0x0000, / 0-43 Left DAC Digital Vol Reg 0x0000, / 0-44 Right DAC Digital V ol Reg 0x0000, / 0-45 Line2L to HPLOUT Vol Reg 0x0000, / 0-46 PGA_L to HPLOUT Vol Reg 0x0080, / 0-47 DAC_L1 to HPLOUT V ol Reg 0x0000,

37、/ 0-48 LINE2R to HPLOUT Vol Reg 0x0000, / 0-49 PGA_R to HPLOUT V ol Reg 0x0000, / 0-50 DAC_R1 to HPLOUT V ol Reg 0x0009, / 0-51 HPLOUT Output Reg 0x0000, / 0-52 LINE2L to HPLCOM Vol Reg 0x0000, / 0-53 PGA_L to HPLCOM V ol Reg 0x0000, / 0-54 DAC_L1 to HPLCOM V ol Reg 0x0000, / 0-55 LINE2R to HPLCOM V

38、 ol Reg 0x0000, / 0-56 PGA_R to HPLCOM V ol Reg 0x0000, / 0-57 DAC_R1 to HPLCOM Vol Reg 0x0000, / 0-58 HPLCOM Output Reg 0x0000, / 0-59 LINE2L to HPROUT V ol Reg 0x0000, / 0-60 PGA_L to HPROUT V ol Reg 0x0000, / 0-61 DAC_L1 to HPROUT Vol Reg 0x0000, / 0-62 LINE2R to HPROUT V ol Reg 0x0000, / 0-63 PG

39、A_R to HPROUT V ol Reg 0x0080, / 0-64 DAC_R1 to HPROUT V ol Reg 0x0009, / 0-65 HPROUT Output Reg 0x0000, / 0-66 LINE2L to HPRCOM V ol Reg 0x0000, / 0-67 PGA_L to HPRCOM V ol Reg 0x0000, / 0-68 DAC_L1 to HPRCOM V ol Reg 0x0000, / 0-69 LINE2R to HPRCOM V ol Reg 0x0000, / 0-70 PGA_R to HPRCOM V ol Reg

40、0x0000, / 0-71 DAC_R1 to HPRCOM V ol Reg 0x0000, / 0-72 HPRCOM Output Reg 0x0000, / 0-73 LINE2L to MONO_LOP/M V ol Reg 0x0000, / 0-74 PGA_L to MONO_LOP/M V ol Reg 0x0000, / 0-75 DAC_L1 to MONO_LOP/M Vol Reg - 0x0000, / 0-76 LINE2R to MONO_LOP/M V ol Reg 0x0000, / 0-77 PGA_R to MONO_LOP/M V ol Reg 0x

41、0000, / 0-78 DAC_R1 to MONO_LOP/M V ol Reg 0x0000, / 0-79 MONO_LOP/M Output Reg 0x0000, / 0-80 LINE2L to LEFT_LOP/M V ol Reg 0x0000, / 0-81 PGA_L to LEFT_LOP/M V ol Reg 0x0080, / 0-82 DAC_L1 to LEFT_LOP/M V ol Reg 0x0000, / 0-83 LINE2R to LEFT_LOP/M V ol Reg 0x0000, / 0-84 PGA_R to LEFT_LOP/M V ol Reg 0x0000, / 0-85 DAC_R1 to LEFT_LOP/M V ol Reg 0x0009, / 0-86 LEFT_LOP/M Output Reg 0x0000, / 0-87 LINE2L to RIGHT_LOP/M V ol Reg 0x0000, / 0-88 PGA_L to RIGHT_LOP/M V ol Reg 0x0000, / 0-89 DAC_L1 to RIGHT_LOP/M V ol Reg 0x0000, / 0-90 LINE2R to RIGHT_LOP/M V ol