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1、附件1：外文资料翻译译文AT89S52主要性能l 与MCS-51单片机产品兼容l 8K字节在系统可编程Flash存储器l 1000次擦写周期l 全静态操作：0Hz33Hzl 三级加密程序存储器l 32个可编程I/O口线l 三个16位定时器/计数器l 八个中断源l 全双工UART串行通道l 低功耗空闲和掉电模式l 掉电后中断可唤醒l 看门狗定时器l 双数据指针l 掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。片上Flash允许程序存储器在
2、系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复
3、位为止。引脚结构方框图VCC : 电源GND : 地P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，p1 输出缓冲器能驱动4个TTL 逻辑电平。对P1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于
4、内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表所示。在flash编程和校验时，P1口接收低8位地址字节。引脚号第二功能P1.0T2（定时器/计数器T2的外部计数输入），时钟输出P1.1T2EX（定时器/计数器T2的捕捉/重载触发信号和方向控制）P1.5MOSI（在系统编程用）P1.6MISO（在系统编程用）P1.7SCK（在系统编程用）P2 口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。对P2端口写“1”时，内部
5、上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX DPTR）时，P2口送出高八位地址。在这种应用中，P2口使用很强的内部上拉发送1。在使用8位地址（如MOVX RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。P3 口：P3口是一个具有内部上拉电阻的8 位双向I/O 口，p2输出缓冲器能驱动4个TTL 逻辑电平。对P3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作
6、为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。在flash编程和校验时，P3口也接收一些控制信号。引脚号第二功能P3.0RXD （串行输入）P3.1TXD （串行输出）P3.2(外部中断0)P3.3 (外部中断0)P3.4T0 （定时器0外部输入）P3.5T1 （定时器1外部输入）P3.6(外部数据存储器写选通)P3.7(外部数据存储器写选通)RST: 复位输入。晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，RST脚输出96个晶振周期的高电平。特殊寄存器AUXR(地址8EH)
7、上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。ALE/：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8位地址的输出脉冲。在flash编程时，此引脚（）也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。这一位置“1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处
8、于外部执行模式下无效。:外部程序存储器选通信号（）是外部程序存储器选通信号。当 AT89S52从外部程序存储器执行外部代码时，在每个机器周期被激活两次，而在访问外部数据存储器时，将不被激活。/VPP:访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，必须接GND。为了执行内部程序指令，应该接VCC。在flash编程期间，也接收12伏VPP电压。XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。XTAL2:振荡器反相放大器的输出端。存储器结构MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。程序存储器：如果引脚接
9、地，程序读取只从外部存储器开始。对于89S52，如果接VCC，程序读写先从内部存储器（地址为0000H1FFFH）开始，接着从外部寻址，寻址地址为：2000HFFFFH。中断AT89S52有6个中断源：两个外部中断（和），三个定时中断（定时器0、1、2）和一个串行中断。这些中断每个中断源都可以通过置位或清除特殊寄存器IE中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON中的TF2和EXF2
10、的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2的标志位TF2在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。参考资料：1ATMEL公司AT89S52的技术手册2深圳市中源单片机发展有限公司AT89C52 Datasheets3复旦大学出版社单片微型机原理、应用和实验张友德等附件2：外文原文AT89S52Features Compatible wi
11、th MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory 1000 Write/Erase Cycles Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Chann
12、el Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off FlagDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atme
13、ls high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system pr
14、ogrammable Flash on a monolithicchip, the Atmel AT89S52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following tandard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog tim
15、er, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power
16、 saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin Config
17、urationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.Port 0 can also be configured to be th
18、e multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri-
19、 fication.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled
20、low will sourcecurrent (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order ad
21、dress bytes during Flash programming and verification.Port PinAlternate FunctionsP1.0T2 (external count input to Timer/Counter 2),clock-outP1.1T2EX (Timer/Counter 2 capture/reload trigger and direction control)P1.5MOSI (used for In-System Programming)P1.6MISO (used for In-System Programming)P1.7SCK
22、(used for In-System Programming)Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are ex
23、ternally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX DPTR). In this application, Port 2 uses strong internal pu
24、llups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-b
25、it bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) be
26、cause of the pullups. Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.Port PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2(ex
27、ternal interrupt 0)P3.3 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6(external data memory write strobe)P3.7(external data memory read strobe)RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This p
28、in drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/Address Latch Enable (ALE) is an output pulse for latching the low byte of
29、the address during accesses to external memory. This pin is also the program pulse input () during Flash programming.In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is
30、skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco
31、- ntroller is in external execution mode.Program Store Enable () is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory./V
32、PP External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be ternally latched on reset. should be strapped to VCC for internal rogram execu
33、tions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the nternal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memor
34、y area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate
35、effect.User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table
36、 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the
37、 six interrupt sources in the IP register.Timer 2 Operating ModesRCLK+TCLKCP/RL2TR2MODE00116-bit Auto-reload01116-bit Capture11Baud Rate Generator0(Off)In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this functio
38、n, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two
39、 machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S5
40、2 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a b
41、it in Special Function Register IE. IE also contains a global disable bit, EA, whichdisables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented.User software should not write 1s to these bit positions, sinc
42、e they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 th
43、at generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Reference data:1. the ATMEL company AT89S52 technical manuals2.Shenzhen Development Co., Ltd. AT89C52 Datasheets source SCM3.Fudan University Press, single-chip microprocessor theory, application and test ZHANG You-de, etc.设计巴巴工作室