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1、XQ4062XL-3CB228N中文资料? 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http:/ .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without no
2、tice.XQ4000X Series Features?Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing)?Ceramic and plastic packages?Also available under the following standard microcircuit drawings (SMD)-XQ4013XL 5962-98513-XQ4036XL 5962-98510-XQ4062XL 5962-98511-XQ4085XL 5962-99575?For more inform
3、ation contact the Defense Supply Center Columbus (DSCC)http:/www.dscc.dla.mis/v/va/smd/smdsrch.html ?Available in -3 speed?System featured Field-Programmable Gate Arrays-SelectRAM? memory: on-chip ultra-fast RAM withsynchronous write option dual-port RAM option -Abundant flip-flops-Flexible function
4、 generators-Dedicated high-speed carry logic -Wide edge decoders on each edge -Hierarchy of interconnect lines -Internal 3-state bus capability-Eight global low-skew clock or signal distributionnetworks?System performance beyond 50 MHz ?Flexible array architecture?Low power segmented routing archite
5、cture ?Systems-oriented features-IEEE 1149.1-compatible boundary scan logicsupport-Individually programmable output slew rate-Programmable input pull-up or pull-down resistors -12 mA sink current per XQ4000XL output ?Configured by loading binary file -Unlimited reprogrammability ?Readback capability
6、 -Program verification-Internal node observability?Development system runs on most common computer platforms-Interfaces to popular design environments-Fully automatic mapping, placement and routing -Interactive design editor for design optimization ?Highest capacity over 180,000 usable gates ?Additi
7、onal routing over XQ4000E-Almost twice the routing capacity for high-densitydesigns?Buffered Interconnect for maximum speed?New latch capability in configurable logic blocks?Improved VersaRing ? I/O interconnect for better Fixed pinout flexibility-Virtually unlimited number of clock signals?Optional
8、 multiplexer or 2-input function generator on device outputs ?5V tolerant I/Os?0.35 m SRAM processIntroductionThe QPRO ? XQ4000XL Series high-performance,high-capacity Field Programmable Gate Arrays (FPGAs)provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cy
9、cle, and inherent risk of a conventional masked gate array.The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs com-bine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed,abundant rout
10、ing resources, and new, sophisticated soft-ware to achieve fully automated implementation of complex, high-density, high-performance designs.Refer to the complete Commercial XC4000XL Series Field Programmable Gate Arrays Data Sheet for more informa-tion on device architecture and timing, and the lat
11、est Xilinx databook for package pinouts other than the CB228(included in this data sheet). (Pinouts for XQ4000XL device are identical to XC4000XL.)QPRO XQ4000XL Series QML High-Reliability FPGAsDS029 (v1.3) June 25, 2000Product SpecificationT able 1: XQ4000XL Series High Reliability Field Progammabl
12、e Gate ArraysNotes:1.Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.2DS029 (v1.3) June 25, 2000XQ4000XL Switching CharacteristicsDefinition of TermsIn the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follo
13、ws:Advance:Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. Values are subject to change. Use as estimates, not for production.Preliminary:Based on preliminary characterization. Further changes are not expected.Unmarked:Specifications no
14、t identified as either Advance or Preliminary are to be considered Final.Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply
15、voltage and junction temperature conditions.All specifications subject to change without notice.Additional SpecificationsExcept for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All speci-f
16、ications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical appli-cations. For design considerations requiring more detailed timing information, see the appropriate family AC supple-ments available on
17、 the Xilinx web site at:http:/ Maximum Ratings(1)1.At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C.2.Input and output measurement threshold is 50% of V CC.4DS029 (v1.3) June 25, 2000XQ4000XL DC Characteristics Over Recommended Operati
18、ng ConditionsPower-On Power Supply RequirementsXilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The slowest ramp-
19、up time is 50ms. Current capacity is not specified for a ramp-up time faster than 2ms. The cur-rent capacity varies linealy with ramp-up time, e.g., an XQ4036XL with a ramp-up time of 25ms would require a capacity predicted by the point on the straight line drawn from 1A at 120s to 500mA at 50ms at
20、the 25ms time mark. This point is approximately 750mA .Notes:1.With up to 64 pins simultaneously sinking 12 mA.2.With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.Notes:1.The XC4085XL fast ramp-up time is 5 ms.2.Devices are guara
21、nteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in alarger initialization current.3.This specification applies to Commercial and Industrial grade products only.4.Ramp-up Time is measured from 0V DC to 3.6V DC . Peak current required lasts
22、 less than 3 ms, and occurs near the internal poweron reset threshold voltage. After initialization and before configuration, I CC max is less than 10 mA.XQ4000XL AC Switching CharacteristicT esting of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All device
23、s are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by t
24、he global clock net.When fewer vertical clock lines are connected, the clock dis-tribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing struct
25、ure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating c
26、onditions (supply voltage and junction temperature)Global Buffer Switching Characteristics6DS029 (v1.3) June 25, 2000XQ4000XL CLB Switching Characteristic GuidelinesT esting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally teste
27、d. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise,and worst-case guaranteed data, use the values reportedby the static timing analyzer (TRCE in the Xilinx Develop-ment System) and back-annotated to
28、 the simulation netlist.All timing parameters assume worst-case operating condi-tions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and expressed in nanosec-onds unless otherwise noted.CLB Switching CharacteristicsCLB Switching Characteristics (Continued)8DS029 (v1.
29、3) June 25, 2000XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation GuidelinesT esting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns.
30、Listed below are representative values. For more specific, more precise,and worst-case guaranteed data, use the values reportedby the static timing analyzer (TRCE in the Xilinx Develop-ment System) and back-annotated to the simulation netlist.All timing parameters assume worst-case operating condi-t
31、ions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and are expressed in nano-seconds unless otherwise noted.Single-Port RAM Synchronous (Edge-Triggered) Write Operation CharacteristicsDual-Port RAM Synchronous (Edge-Triggered) Write Operation CharacteristicsXQ4000XL
32、 CLB Single-Port RAM Synchronous (Edge-Triggered) Write TimingXQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing10DS029 (v1.3) June 25, 2000XQ4000XL Pin-to-Pin Output Parameter GuidelinesT esting of switching parameters is modeled after testing methods specified by MIL-M-38510/605.
33、 All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations a
34、nd normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing ana-lyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided
35、as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanosec-onds unless otherwise noted.Output Flip-Flop, Clock to Out(1,2,3)Notes:1.Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is meas
36、ured usingthe farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parame
37、ter T okpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations.2.Output timing is measured at 50% V CC threshold with 50 pF external capacitive load.12DS029 (v1.3) June 25, 2000Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8Capacitive Load F
38、actorFigure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50pF .For example, if the actual load capacitance is 120pF , add 2.5ns to the specified delay. If the load capacitance i
39、s 20pF , subtract 0.8ns from the specified output delay.Figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control.Notes:1.Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out m
40、aximum delay is measured usingthe farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be ad
41、ded to the AC parameter T okpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations.2.Output timing is measured at 50% V CC threshold with 50 pF external capacitive load.Figure 1: Delay Factor at Various Capacitive LoadsXQ4000XL Pin-to-Pin Input Pa
42、rameter GuidelinesT esting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditi
43、ons (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing ana-lyzer (
44、TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanosec-onds unless otherwise noted.Global Low Skew Clock, Input Setup and Hold Times(1
45、,2)Notes:1.The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.2.Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance anda reference load of one clock pin pe
46、r IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clockloads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.3.IFF = Input Flip-Flop or Latch4.FCL =
47、Fast Capture Latch14DS029 (v1.3) June 25, 2000Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL (1,2)Notes:1.The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.2.Input setup time is measured with the fastest route
48、 and the lightest load. Input hold time is measured using the furthest distance anda reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.3.IFF = Input Flip-Flop or Latch 4.FCL = Fast Capture LatchGlobal Early Clock BUFEs 3