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1、uPD61110DMCOVERPRELIMINARY DATA SHEETMOS Integrated CircuitPD61110/12SECOND GENERATION ENHANCED MULTIMEDIA ARCHITECTUREPROCESSOR FOR DIGITAL TV RECEIVERS/DECODERSDESCRIPTIONThe PD61110/12 devices are members of the second generation of multimedia processors based on NECs Enhanced MultiMedia Architec
2、ture (EMMArchitecture). These devices provide nearly all the functionality required to realise a high performance and cost-effective digital set-top box or integrated digital TV.FEATURESX MPEG1 and MPEG2-TS/PS compliant XHigh performance MIPS32? 4Kc? main CPU coreXHigh performance MIPS32? 4Km? sub-
3、CPU coreXIntegrated DVB descrambling with family options for Irdeto and Multi2X 36 PID filters, 32 section filtersXVideo Outputs: 4 DACs for RGB, component video, S-video and composite output with support for PAL, NTSC and SECAM X4 graphics planesXSupport for Macrovision? analog video copy protectio
4、n (PD61112 only)X Audio Output: 2-channel PCM and SPDIF XPeripherals support?two fast UARTs with 16byte FIFOs ?I 2C interface ?infrared receiver?three wire clocked serial interfaceX System timers, RTC and Watchdog timer XMotorola/Intel Bus.ORDERING INFORMATIONPart NumberDescription RemarksPD61110 GD
5、-10x-LML Standard part.Please contact NEC for details of other variants.PD61112 GD-10x-LMLMacrovision support.The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all devices/types are available in every
6、country. Please check with the local NEC representative for availability and additional information.Document No. S16829EE1V7DS001st edition 1.7P 2003-12-04? NEC Electronics Corporation 2003PD61110/122Preliminary Data Sheet S16829EE1V7DS00PD61110/12FEATURE LISTMain ProcessorX High Performance MIPS32
7、4Kc Jade CPU coreX32bit RISC MIPS architectureX Supports the MIPS-I, MIPS-II and a subset of the MIPS-III instruction setsX4KByte instruction cache, 4KByte data cacheX 2 way cache accessingX EJTAG debug supportSub-ProcessorX High Performance MIPS32 4Km Jade CPU core for audio MPEG decodingX4KByte in
8、struction cache, 4KByte data cacheX8KByte scratch-pad memory support Unified Memory InterfaceX Supports 16bit bus width SDRAMX Unified CPU/MPEG/Graphics memoryX Supports data rates up to 133MHzX Supports 8, 16, 32 or 64Mbytes total memoryROM/GIO InterfaceX Total address area 64Mbyte for ROMX Support
9、s normal, page, burst and flash ROM X Supports NOR and NAND flash ROMX 2 chip select signals for ROMX128MByte total address area for GIOX 2 chip select signal for GIOX PCMCIA support (16-bit PC Card only) DMAX Supports memory-to-memory DMA transfers Programmable TS De-multiplexerX Single stream inpu
10、t configurable as a parallel or serial portX Supports MPEG2-TSX Maximum input bit rate 100Mbit/secX High Speed Data port output for external IEEE1394 link devicesX36 PID filters:? 1 Video PID? 2 Audio PIDs? 1 PCR PID?32 general PIDsX32 section filters (8-Byte/16-byte depth) DescramblerX Supports dec
11、ryption with 16 key-pairs MPEG video decoderX MPEG-2 MPML standard compliantX Supports MPEG-1 and -2 elementary streamsX Trick play: fast, slow, freeze and step Audio ProcessorX MPEG-1 and -2, layer 1 and 2X PCM L+R audio outputX SPDIF outputX Test-tone and MixingGraphics engineX2-D image data trans
12、ferX Colour space conversion: RGB32 to YCbCr X Colour expansionDisplayX 4 graphics planes: background colour, live video and two OSD planesX256-level alpha blending between all planes X Real time scaler for the live video plane supporting independent horizontal andvertical scale factors between 4 an
13、d 1/4X Anti-flicker filtering for OSDX Independently blended output for VCRPreliminary Data Sheet S16829EE1V7DS003PD61110/124Preliminary Data Sheet S16829EE1V7DS00PD61110/12CONTENTS1FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1Overview . . . . . .
14、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.4Memory Interfaces . . . . . . .
15、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4.1Unified Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4.2ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4.3General IO Interface . . . . . . . . . . . . . . . .
16、. . . . . . . . . . . . . . . . 81.5Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.5.1Programmable transport de-multiplexer . . . . . . . . . . . . . . . . . . . . . . 81.5.2DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17、. . . . 81.5.3MPEG video decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.5.4Audio controller module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.5Graphics engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.6Display module .
18、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.7Video encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.6Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.7Timers. . . . . . . . . . . . . . . . .
19、. . . . . . . . . . . . . . . . . . . . . . . . . . 101.8Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.9Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2PIN SPECIFICATIONS . . . . . . . . . . . . . . . . .
20、 . . . . . . . . . . . . . . . . . . . . . 112.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1.2Boot Configuration . . . . . . . . . . . . . . . . . . . . . .
21、. . . . . . . . . . 122.1.3Strap Pin Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.4Selecting multiple interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22、172.2.1Global Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.2Unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2.3Functions with exclusive use of pins . . . . . . . . . . . . . . . . . . . . . . . 192.2.4Functions which share p
23、ins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.1Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2Recommended Operating Conditions . . . . . . . .
24、. . . . . . . . . . . . . . . . . . 313.2.1Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.3DC Characteristics General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4DC Characteristics Unified Memory Interface . . . . . . . . . . . . . . . . . .
25、 . . . 313.5DC Characteristics I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.6DAC Characteristics Analog Video Outputs . . . . . . . . . . . . . . . . . . . . . . 323.6.1NTSC Composite output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.6.2NTSC Y/C output .
26、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.6.3NTSC Y/Pb/Pr output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.6.4NTSC RGB output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.6.5PAL Composite output . . . . . . . . . . . . . . . . . . .
27、. . . . . . . . . . 353.6.6PAL Y/C output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.6.7PAL Y/Pb/Pr output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.6.8PAL RGB output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Preliminary Data
28、Sheet S16829EE1V6DS005PD61110/126Preliminary Data Sheet S16829EE1V6DS00PD61110/12Preliminary Data Sheet S16829EE1V6DS0071FUNCTIONAL DESCRIPTION 1.1OverviewThe PD61110/12 devices integrate the functions of a programmable TS de-multiplexer, a DMA controller, an MPEG video decoder, a programmable audio
29、 controller, graphics and display engines, a video encoder and DACs, and various interfaces to support peripheral modules. The device has been designed with a memory interface using glueless logic supporting 16-bit bus width SDRAM. The PD61110/12 incorporates two processors, two main buses and a per
30、ipherals bus. Both processors are MIPS32 cores and both can access all modules within the device.1.2Block Diagram1.3ProcessorsThe PD61110/12 have one MIPS32 4Kc core for the main CPU and one 4Km core for the sub-CPU.These are high performance RISC CPUs. Overall system efficiency is promoted by the i
31、ncorporation of on-chip 4KByte instruction and 4KByte data caches.The main CPU is for running user programs and supports the entire MIPS II instruction set plus MIPS III 32bit instructions for the MDU (Multiply Divide Unit), TLB (Translation Lookaside Buffer), MMU (Memory Management Unit) and MAC (M
32、ultiply Accumulate Unit).The sub-CPU supports the MIPS II instruction set and incorporates an 8KByte scratch-pad memory. The primary function of the sub-CPU is audio decoding.A dedicated ROM interface keeps the memory bus free during instruction fetches which helps to keep bus efficiency high for ot
33、her bus masters. A unified memory architecture is used to minimise system memory costs. Development time is minimised by the provision of an enhanced JTAG (EJTAG)debugging interface.PD61110/128Preliminary Data Sheet S16829EE1V6DS00PD61110/12Preliminary Data Sheet S16829EE1V6DS0091.5.4Audio controlle
34、r moduleThe audio controller handles layers 1 and 2 for MPEG-1 and -2 and can output stereo PCM and SPDIF with IEC60958 encoding. A test-tone generator and a mixing facility with separate left and right attenuation are also included.1.5.5Graphics engineThe graphics engine incorporates a 2-D bit-blit
35、ter with a colour space conversion function supporting the conversion of RGB32 format data to YCbCr 4:2:2 format. Colour space conversion may be used to support scaling of OSD data by using the real-time scaler for the still plane in the display module which only accepts YCbCr 4:2:2 or 4:2:0 format
36、data. The graphics engine also supports colour expansion which may be used to increase the bit-depth of one or two bit font data.1.5.6Display moduleThe display module handles four planes: live video, OSD1, OSD2 and a background colour plane. The video plane is for decoded MPEG video. Full 256-level
37、alpha blending between all four planes is supported and the display module also incorporates a capture function for grabbing live video frames.There is a real-time scaler for the video plane supporting horizontal and vertical scale factors from 1/4to 4 handling both 4:2:2 and 4:2:0 format data. Hori
38、zontal scaling uses a 7-tap filter. Vertical scaling uses a 5-tap filter for luma and a 3-tap filter for chroma.The OSD planes support CLUT and RGB formats. CLUT modes are 1, 2, 4 and 8bpp; RGB modes are 12bpp plus 4bit alpha, 15 plus 1bit alpha, 16bpp and 32bpp. Anti-flicker filtering for the OSD p
39、lanes is provided by a 3-tap filter. The OSD2 plane can also be used to provide a software cursor function.1.5.7Video encoderThe video encoder and sync generator modules support NTSC, PAL and SECAM video standards including PAL-M, PAL-N and PAL-Nc.There are 4 DACs for analog video output providing f
40、or composite (CVBS), S-video (Y/C) and component video (RGB or YPbPr/YCbCr). A digital output compliant with Rec.656 is also available. The encoder includes a VBI data insertion function for Closed Captions, Teletext, WSS, VPS, CGMS and Video ID.Macrovision analog copy protection is available as a f
41、amily option in the PD61112.1.6PeripheralsPeripherals are supported by:X Two asynchronous 16550 compatible UARTs with 16Byte FIFOs.X A 3-wire Clocked Serial Interface supporting operation stop mode and 3-wire serial I/O mode.X One multi-master, I 2C compatible interface.XAn infrared receiver interfa
42、ce an input capture timer that measures the interval between adjacent edges of the demodulated signal from an IR detector/amplifier.XA general purpose, programmable pin interface of up to 45 pins.These pins are shared with other peripherals. If more general purpose I/Os are needed than are left free
43、 after all required optional interfaces are enabled, it is possible to use spare ROM address pins with an external data latch such as a TTL 74574. Two sets of clock and enable signals are available to control such external latches.PD61110/1210Preliminary Data Sheet S16829EE1V6DS00PD61110/12Prelimina
44、ry Data Sheet S16829EE1V6DS00112PIN SPECIFICATIONS 2.1Pin Configuration2.1.1OverviewThe PD61110/12 is designed for maximum flexibility of pin assignment with a minimum device cost.Sixteen of the 216 pins are used for strapping (system configuration at start-up or reset). The state of these strap pin
45、s at reset decide the configuration of the following:X Processor clock speed X Processor endian mode X Processor merge modeX Pin configuration for the enhanced JTAG interface X Memory clock speed X ROM interface endian mode X ROM type and area used for booting XROM bus width.After start-up the major
46、ity of the interfaces may be enabled using a register in the Host Interface block.In addition to the power, ground, JTAG, test and system pins, the interfaces always available are:X unified memory X audio out X I 2C interface Xanalog video out.The ROM/GIO Interface block supports external ROM by def
47、ault but can be configured to support NAND flash ROM, PCMCIA cards (not CardBus) and a General I/O (GIO) interface.The remainder of the interfaces share pins with the Programmable Pin Port and with each other. These are:X one serial or one parallel TS inputX a High Speed Data output (HSD) for AV dat
48、a X two fast UARTs with FIFOs X a three wire clocked serial interface X an infrared interface input X a digital video output Xfour I/Os for timers.Any pins of the Programmable Pin Port (PPORT) not used by enabled interfaces may still be used as general purpose I/O pins. Each pin can be configured independently to be an input or output.PD61110/1212Preliminary Data SheetS16829EE1V6DS00PD61110/12Preliminary Data Sheet S