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1、设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额 5 元，并支持找零。要求： (1)用状态机方法设计；综合。( 2)用 Verilog HDL 语言设计，用 Modelsim 软件做功能仿真，用 Quartus II (3)将设计代码和仿真代码写在作业本上。module zhaoling(clock,reset,A,ticket,change);input clock,reset;input 2:0 A;output ticket;output 2:0 change;reg 2:0 state;reg ticket;reg 2:0 change;parametersta_0
2、=3'd0,sta_1=3'd1,sta_2=3'd2,sta_3=3'd3,sta_4=3'd4, sta_5=3'd5;always (posedge clock or negedge reset) if(!reset)begin state<=sta_0; ticket<=0; change<=0; end elsecase(state)sta_0:if(A = 1)begin state = sta_1; ticket<=0; change<=0; end else if(A = 2)begin state
3、= sta_2; ticket<=0; change<=0; end else if(A = 5)begin state = sta_5; ticket<=1; change<=0; end elsebegin state = sta_0; ticket<=0; change<=0; end sta_1:if(A = 1)begin state = sta_2; ticket<=0; change<=0; endelse if(A = 2)begin state <= sta_3; ticket<=0; change<=0; e
4、ndelse if(A = 5)begin stateelse<=sta_0; ticket<=1;change<=1; endbegin state sta_2:if(A = 1)begin stateelse if(A = 2)begin state <= sta_4; ticket<=0;else if(A = 5)begin stateelse<=<=<=sta_1; ticket<=0;sta_3; ticket<=0;sta_0; ticket<=1;begin state sta_3:if(A = 1)begin
5、stateelse if(A = 2)begin state <= sta_5; ticket<=1;else if(A = 5)begin stateelse<=<=<=sta_2; ticket<=0;sta_4; ticket<=0;sta_5; ticket<=1;begin state sta_4:if(A = 1)begin stateelse if(A = 2)<=<=sta_3; ticket<=0;sta_5; ticket<=1;begin state <= sta_5; ticket<=1
6、;else if(A = 5)begin stateelse<=sta_5; ticket<=1;begin state sta_5:if(A = 1)begin stateelse if(A = 2)begin state <= sta_2; ticket<=0;else if(A = 5)begin state <= sta_5; ticket<=1; else<=<=sta_4; ticket<=0;sta_1; ticket<=0;begin state <= sta_5; ticket<=0; default:
7、state <= sta_0;endcaseendmoduletimescale 1ns/1ns module test;change<=0; endchange<=0; endchange<=0; endchange<=2; endchange<=0; endchange<=0; endchange<=0; endchange<=3; endchange<=0; endchange<=0; endchange<=1; endchange<=4; endchange<=0; endchange<=0; e
8、ndchange<=0; endchange<=0; endchange<=0; endreg Clock,Reset; reg 2:0 A; wire Ticket;wire 2:0 Change;initialbeginA=0;Reset = 1;Clock = 0;Reset = 0; #10 Reset = 1; endalways #10 Clock<=Clock;initialbegin#20 A = 1;#20 A = 1;#20 A = 1;#20 A = 1;#20 A = 1;#20 A = 1;#20 A = 2;#20 A = 2;#20 A = 2;#20 A = 2;#20 A = 1;#20 A = 2;#20 A = 1;#20 A = 2;#20 A = 2;#20 A = 2;#20 A = 2;#20 A = 5;endzhaolingm(.clock(Clock),.reset(Reset),.A(A),.ticket(Ticket),.change(Change); endmodule（资料素材和资料部分来自网络，供参考。可复制、编制，期待你的好评与关 注）