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1、Signal Integrity and PCB layout considerationsfor DDR2-800 Mb/s and DDR3 MemoriesFidus Systems Inc.900, Morrison Drive, Ottawa, Ontario, K2H 8K7, CanadaChris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed BokhariSessi on # 8.13Presented atcadEncE designer networkLIVSilicon Valle
2、y 2007AbstractThe paper addresses the challe nge of meet ing Signal In tegrity (SI) and Power In tegrity (PI) requireme nts of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conven ti onal tech no logy.
3、 Some desig n guideli nes have bee n provided.1. In troduct ionDDR2 usage is com mon today with a push towards higher speeds such as 800 Mbps 1 and more recen tly, 1066 Mbps. DDR3 2 targets a data rate of 1600 Mbps. From a PCB impleme ntatio n stan dpo int, a primary requireme nt is delay matchi ng
4、which is dictated by the tim ing requireme nt. This brings into it a nu mber of related factors that affect waveform in tegrity and delay. These factors are in terdepe ndent, but where a dist in ctio n can be made, they can be termed pCb layer stackup and impeda nee, in terc onnect topologies, delay
5、 matchi ng, cross talk, PI and timi ng. Cade nee ALLEGRO?SI-230 and An soft' s HFSS? are used in all computatio ns.| VDD / VrefClockAddressADDR<15,0>VDD / Vtt / VrefCKP,CKNComma nd/ Con trol DataStrobe (differe ntial) DataMaskDataCon trollerCKE, CS, ODT, RAS,CAS,WE,BA0-2DM0,DM1,DM2,DM3DQS0
6、,DQS1,DQS2,DQS3DQ <7,0>, DQ<15,8>,DQ<23,16>, DQ<31,24>MemoryMax Clock Freq. (MHz)/Data rate(Mbps)533/1066800/1600Power Requireme nt1 VDD (Volts)1.8 +/- 0.11.5 +/- 0.075Vtt (Volts)0.9 +/- 0.040.75 +/- TBD1:Vref (Volts)0.9 +/- 0.0180.75 +/- 0.015In put ThresholdsVih/Vil (Volts)
7、0.9 +/- 0.20.75 +/- 0.175Delay Match ing Requireme nt1 Match ADDR/CMD/CNTRL to Clock tightlyYesYesMatch DQ<7,0>, DM0 to DQS0 tightlyYesYesMatch DQ<15,8>, DM1 to DQS1 tightlyYesYesMatch DQ<22,16>, DM2 to DQS2 tightlyMatch DQ<31,23>, DM3 to DQS3 tightlyYesYesYesYesMatch DQS0-3
8、to Clock looselyYesNot requiredDDR2DDR3Tech no logyTable 1: Comparison of DDR2 and DDR3 requireme ntsSig nals com mon to both tech no logies and a gen eral comparis on of DDR2 and DDR3 is show n in Table 1. It must be no ted that“ matchi ng ” in cludes cases where the clock net may be made Ion ger (
9、termed DELTA inALLEGRO SigXP). We have assumed a con figuration comprisi ng a Con troller and two SDRAMs in most illustrati ons that follow.2. PCB Layer stackup and impeda neeIn a layer constrained implementation, a 4 layer PCB (Figure 1) is a minimum with all routing on TOP and BOTTOM layers. One o
10、f the intern al layers will be a solid ground pla ne (GND). The other internal pla ne layer is dedicated to VDD. Vtt and Vref can be derived from VDD. Use of a 6-layer PCB makes the implementation of certa in topologies easier. PI is also enhanced due to the reduced spaci ng betwee n power and GND p
11、la nes.The in terc onnect characteristic impeda nee for DDR2 impleme ntati on can be a con sta nt. A sin gle-e nded trace characteristic impedance of 50 Ohms can be used for all single-ended signals. A differential impedance of 100 Ohms can be used for all differe ntial sig nals, n amely CLOCK and D
12、QS. Further, the term in ati on resistor pulled up to VTT can be kept at 50 Ohms and ODT sett ings can be kept at 50 Ohms.In the case of DDR3 however, sin gle en ded trace impeda nces of 40 and 60 Ohms used selectively on loaded secti ons of ADDR/CMD/CNTRL n ets have bee n found to be adva ntageous.
13、 Further, the value of the term in ati on resistor pulled up to Vtt n eeds to be optimized in comb in ati on with the trace impeda nce through SI simulatio ns. Typically, it is in the range 30 70 Ohms. The differe ntial trace impeda nce can remai n at 100 Ohms.Figure 1 : Four and Six layer PCB stack
14、up3. In terc onnect TopologiesIn both cases of DDR2 and DDR3, DQ, DM and DQS signals are point-to-point and do not need any topological con sideratio n. An exceptio n is in the case of multi-ra nk Dual In Line Memory Modules (DIMMs). Waveform integrity is also easily addressed by a proper choice of
15、drive strengths and On Die Termination (ODT). The ADDR/CMD/CNTRL sig nals, and sometimes the clock sig nal will in volve a multipo int connection where a suitable topology is n eeded. Possible choices are in dicated in Figure 2 for cases in volvi ng two SDRAMs. The Fly-By Topology is a special case
16、of a daisy cha in with a very short or no stub.For DDR3, any of these topologies will work, provided that the trace len gths are mini mized. The Fly-by topology shows the best waveform in tegrity in terms of an in creased no ise margi n. This can be difficult to impleme nt on a4-layer PCB and the n
17、eed for a 6-layer PCB arises. The daisy cha in topology is easier to impleme nt on a 4 layer PCB. The tree topology on the other hand requires the length of the branch AB to be very close to that of AC (Figure 2). Enforcing this requireme nt results in the n eed to in crease the len gth of the bran
18、ches which affects waveform in tegrity. Therefore, for DDR3 impleme ntatio n, the daisy cha in topology with mini mized stubs proves to be best suited for 4-layer PCBs.For DDR2-800 Mbps any of these topologies are applicable with the dist inction betwee n each other being less dramatic. Aga in, the
19、daisy cha in proves to be superior in terms of both impleme ntati on as well as SI.Where more tha n two SDRAMs are prese nt, ofte n, the topology can be dictated by con stra ints on device placeme nt. Figure 3 shows some examples where a topology could be chose n to suit a particular comp onent plac
20、eme nt. Of these, only A and D are best suited for 4-layer PCB impleme ntatio n. Agai n, for DDR2-800 Mbps operations all topologies yield adequate waveform integrity. For a DDR3 implementation, in particular at 1600 Mbps, only D appears to be feasible.Tree topologytRt VVIFly-By topologyRtFigure 2:
21、ADDR/CMD/CNTRL topologies with 2 SDRAMSRFigure 3: ADDR/CMD/CNTRL topologies with four SDRAMS4. Delay matchi ngImplementing matched delay is usually carried out by bending a trace in a trombone shape. Routing blockage may require layer jump ing. Unfortun ately, while physical in terc onnect len gths
22、can be made ide ntical in layout, electrically, the two configurations shown in Figure 4 will not be the same.The case of tromb one delay has bee n well un derstood, and the case of a via is obvious. The delay of a trombone trace is smaller tha n the delay of a straight trace of the same cen ter-li
23、ne len gth. In the case of a via, the delay is more than that of a straight microstrip trace of length equal to the via length. The problem can be resolved in two differe nt ways. In the first approach, these values can be pre-computed precisely and take n into acco unt while delay match ing. This w
24、ould become a tedious exercise which could perhaps be eased with userStraight traceTromb one traceL1 + L2 + L3+ L4 + L5Via cross sect ional viewStraight trace:L2L1+ L2 + L3L3defined constraints in ALLEGRO 16.0. In the second approach, one would use means to reduce the disparity to an acceptable leve
25、l.俪 H HIL|WF_lili£ idQ .曲。礼甲TLM2 .I3.MFLM$jio4.1 站 22 站 站 帖 陽 加 11.1 讣 1Jmi(M|Figure 4: Illustrati on of Tromb one traces and ViasPEF DR帕HIE叫臨perRJ "Mt Ui QmFigure 5: Circuit for estimati on of tromb one effect and result ing waveforms.Con sider the case of a tromb one trace. It is known t
26、hat the disparity can be reduced by in creas ing the len gth of L3 (Figure 4). Details can be found in reference 3. A simulati on topology can be set up in SigXP to represe nt parallel arms of a trombone trace as coupled lines. A sweep simulation is carried out with L3 (S in Figure 5) as a variable
27、and the largest reas on able value that reduces the delay differe nee with respect to a reference trace is selected. For microstrip traces, L3 > 7 times the distance of the trace to ground is needed.Delay values are affected in a tromb one trace due to coupli ng betwee n parallel trace segme nts.
28、 Ano ther way to reduce coupling without increasing the spacing is to use a saw tooth profile. The saw tooth profile shows better performa nce as compared to a tromb one although it even tually ends up requiri ng more space. In either case, it is possible to estimate the effect on delay precisely by
29、 using a modified equation for the computation of the effective trace len gth 3. This would n eed to be impleme nted as a user defi ned con stra int in ALLEGRO.Con sider the case of a through hole via on the 6 layer stackup of Figure 2. Ground vias placed close to the signal vias play an important r
30、ole in the delay. For the illustration, the microstrip traces on TOP and BOTTOM layers are 150 mils long, and 4 mils wide. The via barrel diameter = 8 mils, pad diameter is 18 mils and the antipad diameter is 26 mils.Three differe nt cases are con sidered. In the first case, the in terc onnect with
31、via does not have any ground vias in its immediate neighborhood. Return paths are provided at the edges of the PCB 250 mils away from the signal via. In the second case, a reference straight microstrip trace of length = 362 mils is considered. The third case is the same as case 1 with four gro und v
32、ias in the n eighborhood of the sig nal via. Computed s-parameters with 60 Ohm normalization are shown in Figure 6. It can be seen that the use of 4 ground vias surrounding the signal via makes its behavior more like a uniform impedance transmission line and improves the s21 characteristic. In the a
33、bse nce of a return path in the immediate n eighborhood, the via impeda nce in creases. For the prese nt purpose, it is importa nt to know the result ing impact on the delay.A test circuit is set up similar to Figure 5. The driver is a lin ear source of 60 Ohms output impeda nce and outputs a trapez
34、oidal signal of rise time = fall time = 100 ps and amplitude = 1V. It is connected to each of the 3 interconnects shown in Figure 6 and the far end is terminated in a 60 Ohm load. The excitation is a periodic sig nal with a freque ncy of 800 MHz. The time differe nce betwee n the driver waveform at
35、V = 0.5 V and the waveform at the receiver gives the switched delay.Results are illustrated in Figure 7 where only the rising edge is show n. It can be see n that the delay with four n eighbori ng gro und vias differs from that of the straight trace by 3 ps. On the other hand, the differe nce is 8 p
36、s for the interconnect with no ground vias in the immediate neighborhood.It is therefore clear that increasing the ground via density near signal vias will help. However, in the case of 4 layer PCBs, this will not be possible as the sig nal traces adjace nt to the Power pla ne will be refere need to
37、 a Power pla ne. Con seque ntly, the sig nal retur n path would depe nd on decoupli ng. Therefore, it is very importa nt that the decoupli ng requireme nt on 4 layer PCBs addresses retur n paths in additi on to meet ing power in tegrity requireme nts.The clock net is differential in both DDR2 and DD
38、R3. In DDR2, DQS can be either single ended or differential although it is usually implemented as differential at higher data rates. The switched delay of a differential trace is less than that of a single ended trace of identical length. Where timing computations indicate the need, the clock and DQ
39、S traces may n eed to be made longer than the correspo nding ADDR/CMD/CNTRL nets and DATA nets. This would en sure that the clock and DQS tran sitio ns are cen tered on the associated ADDR/CMD/CNTRL nets and DQ n ets.Since DQ and DM n ets run at the maximum speed, it is desirable that all of these n
40、 ets in any byte lane be routed iden tically, preferably without vias. Differen tial n ets are less sen sitive to disc on ti nu ities and where layer jump ing is n eeded, the DQS and CLOCK n ets should be con sidered first.-10-15§ -20-25-30-35-40Sil234567Frequency (GHz)Figure 6: s-parameters of
41、 in terc onn ects with vias (60 Ohm no rmalizati on)Figure 7: Driver and Receiver waveforms for the 3 cases of Figure 6. (Plot colors corresp ond)5. CrosstalkCross talk con tributes to delay un certa inty being sig ni fica nt for microstrip traces. This is gen erally reduced by in creas ing the spac
42、 ing betwee n adjace nt traces for long parallel runs. This has the drawback of in creas ing the total trace len gth and therefore a reas on able value must be chose n. Typically the spaci ng should be greater tha n twice the trace dista nce to gro und. Aga in, gro und vias play an importa nt role.
43、Near and far end coupli ng levels are illustrated in Figure 8. Use of multiple ground vias reduces coupling levels by 7 dB. To derive the in terc onnect budget, a simulati on of a victim trace with two aggressors on both sides is adequate. Using a periodic excitati on on all n ets will yield the cro
44、ss talk in duced jitter. Using a pseudo ran dom excitati on on all n ets will show the effect of both cross talk as well as data depe nden cies. Time doma in results are not show n here, but it is easily done by setti ng up a 5 coupled line circuit in SigXP with the spac ing betwee n traces set up f
45、or sweep ing. Reas on able spaci ng values that keep the jitter in the waveform due to both cross talk as well as patter n depe ndence at an acceptable level are chose n.Frequency (GHz)Figure 8: s-parameters of coupled traces (60 Ohm no rmalizati on)6. Power In tegrityPower In tegrity here refers to
46、 meeti ng the Power supply tolera nee requireme nt un der a maximum switch ing con diti on. Failure to address this requireme nt properly leads to a nu mber of problems, such as in creased clock jitter, i ncreased data depe ndent jitter, and in creased cross talk all of which even tually reduce tim
47、ing marg ins.The theory for decoupli ng has bee n very well un derstood and usually starts with the defi niti on of a“ tareimpedanee ” as 4Z t arg etVoltage toleranee Transient Current(1)An importa nt requireme nt here is kno wledge of the tran sie nt curre nt un der worst case switch ing con diti o
48、n. A sec ond importa nt requireme nt is the freque ncy ran ge. This is the range of freque ncies over which the decoupli ng n etwork must en sure that its impeda nee value is equal to or below the required target impeda nee. On a prin ted circuit board, capacita nee created by the Power-Gro und san dwich and the decoupli ng capacitors n eeds to han dle a minimum freque ncy of 100 kHz up to a maximum freque ncy of 100-200 MHz. Freque ncies below 100 kHz are easily addressed by the bulk capacita nee of the volt