《SPI数据格式.doc》由会员分享，可在线阅读，更多相关《SPI数据格式.doc（8页珍藏版）》请在三一文库上搜索。
1、Synchronous Serial Interface君正I Ingenlc23.5 Data FormatsFour sig nals are used to tran sfer data betwee n the processor and exter nal peripheral. The SSI supports three formats: Motorola SPI, Texas In strume nts SSP, and Nati onal Microwire. Althoughthey have the same basic structure the three forma
2、ts have sig ni fica nt differe nces, as described below.SSI_CE_/SSI_CE2_ varies for each protocol as follows:? For SPI and Microwire formats, SSI_CE_/SSI_CE2_ fun ctio ns as a chip select to en able the exter nal device (target of the tran sfer), and is held active-low duri ng the data tran sfer.? F
3、or SSP format, this signal is pulsed high for one serial bit-clock period at the start of each frame.SSI_CLK varies for each protocol as follows:For Microwire, both tran smit and receive data sources switch data on the falli ng edge of SSI_CLK, and sample incoming data on the rising edge.For SSP , t
4、ransmit and receive data sources switch data on the rising edge of SSI_CLK, and sample incoming data on the falli ng edge.For SPI, the user has the choice of which edge of SSI_CLK to use for switch ing outgo ing data, and for sampli ng incoming data. In additi on, the user can move the phase of SSI_
5、CLK, shifting its active state one-half period earlier or later at the start and end of a frame.While SSP and SPI are full-duplex protocols, Microwire uses a half-duplex master-slave messag ing protocol. At the start of a frame, a 1 or 2-byte con trol message is tran smitted from the con troller to
6、the peripheral. The peripheral does not send any data. The peripheral interprets the message and, if it is a READ request, resp onds with requested data, one clock after the last bit of the request ing message.The serial clock (SSI_CLK) only toggles during an active frame. At other times it is held
7、in an in active or idle state, as defi ned by its specified protocol.23.5.1 Motorola ' s SPI Format Details23.5.1.1 Ge neral Sin gle Tran sfer FormatsThe figures below show the tim ing of gen eral sin gle tran sfer format.497Jz4755 Multimedia Application Processor Programming Manual, Revision 1.
8、0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.君正IngonicSynchronous Serial InterfaceFigure 23-1 SPI Si ngle Character Tran sfer Format (PHA = 0)Figure 23-2 SPI Si ngle Character Tran sfer Format (PHA = 1)For SSICR1.PHA = 0, when SSICR1.TFVCK = B ' 00, hardware ensures
9、the first clock edge appears one SSI_CLK period after SSI_CE_ / SSI_CE2_ goes valid; when SSICR1.TCKFI = B' 00, hardwareen sures the SSI_CE_ / SSI_CE2_ negated half SSI_CLK period after last clock change edge; whe n SSICR1.TFVCK MB ' 00 or SSICR1.TCKFRB ' 00, 1/2/3 more clock cycles are
10、inserted.For SSICR1.PHA = 1, when SSICR1.TFVCK = B ' 00, hardware ensures the first clock edge appearshalf SSI_CLK period after SSI_CE_ / SSI_CE2_ goes valid; when SSICR1.TCKFI = B' 00, hardwareen sures the SSI_CE_ / SSI_CE2_ n egated one SSI_CLK period after last clock cha nge edge; whe n S
11、SICR1.TFVCK MB ' 00 or SSICR1.TCKFRB ' 00, 1/2/3 more clock cycles are inserted.498Jz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceData is sampled from SSI_DR at every
12、 risi ng edge (when PHA = 0, POL = 0 or PHA = 1, POL = 1) or at every falling edge (when PHA = 0, POL = 1 or PHA = 1, POL = 0). According to SPI protocol, input data on SSI_DR should be stable at every sample clock edge.Drive data onto SSI_DT at every risi ng edge (when PHA = 0, POL = 1 or PHA = 1,
13、POL = 0) or at every falli ng edge (when PHA = 0, POL = 0 or PHA = 1, POL = 1).23.5.1.2 Back-to-Back Tran sfer FormatsSSI CLK(POL=0, PHA=0 or POL=1, PHA=1)SSI CLK(POL=1, PHA=0or POL=0, PHA=1)SSI CE / SSI CE2(SSICR1.FRMHLn = 0SSI DTSSI DRSSI GPCGPCLSbXmSBX LSB X_ri3XM!b LSB X MsQ 乂 LSB XFigure 23-3 S
14、PI Back-to-Back Tran sfer FormatFor Motorola ' s SPI format transfers those continuous characters are exchanged during SSI_CE_ /SSI_CE2_ bei ng valid, the timi ng is illustrated in the figure (SSICR1. LFST = 0).Back-to-back tran sfer is performed as tran smit-o nly/full-duplex operati on whe n t
15、ran smit-FIFO is not empty before the completion of the last character' s transfer or performed as receive-only operation.499君正I Ingenilc23.5.1.3 Frame In terval Mode Tra nsfer FormatWhen in interval mode (SSIITR. IVLTM 丰 O' ), SSI always wait for an interval time (SSIITR.IVLTM), tran sfer f
16、ixed nu mber of characters (SSIICR), the n repeats the operati on.When SSICR0.RFINE = 1, if tran smit-FIFO is still empty after the in terval time, receive-o nly tran sfer will occur.Duri ng in terval-wait time, SSI stops SSI_CLK, and whe n SSICR1.ITFRM =0 it negates theSSI CE / SSI CE2 , when SSICR
17、1TFRM = 1 it keeps asserting the SSI CE / SSI CE2 .For tran sfers fini shed with tran smit-FIFO empty, if the SSI tran smit-FIFO is empty before fixed number of characters being loaded to transfer (SSICR1.UNFIN must be 1), then the SSI will set SSISR.UNDR = 1; if enabled, it' ll send out a SSI u
18、nderrun interrupt. At the same time, SSI will hold the SSI CE / SSI CE2 and SSI CLK signals at current status and wait for the transmit-FIFOfilling. The SSI will continue transfer after transmit-FIFO being filled. The SSI always stops after completion of fixed number of characters' tran sfer (SS
19、ICR1.UNFIN must be 0) with tran smit-FIFO empty.'tran sfer.For transfers finished by SSICR0.RFINC being valid set, the SSI will stop after finished current character transfer and needn' t wait for a whole completion of fixed number of charactersMSB 'LSBMSB LSBTwo Interval transfer mode a
20、re illustrated in the following figures. In these timing diagram, SSICR1.PHA = 0, SSICR1.POL = 0 and SSIICR = 0.SSI_CLK SSI_CE_/ SSI_CE2_ (SSICR1.FRMHLn =0)SSI_DTSSI_DRSSI_GPC Figure 23-4 SPI Frame In terval Mode Tran sfer Format (ITFRM = 0, LFST = 0)500Jz4755 Multimedia Application Processor Progra
21、mming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial Interface君正Ingeriic23.5.2 TI ' s SSP Format DetailsIn this format, each tran sfer begi ns with SSI_CE_ pulsed high for one SSI_CLK period. Then both master and slave drive data a
22、t SSI_CLK' s rising edge and sample data at the falling edge. Data aretransferred with MSB first or LSB first. At the end of the transfer, SSI_DT retains the value of the last bit sent through the next idle period.501Jz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyrig
23、ht? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceSSI CLKSSI CESSI DT1 SSI_CLK period1 SSI_CLK periodPJIOSSI DRLS君正IngonicFigure 23-7 TI ' s SSP Back-to-back Transfer Format23.5.3 National Microwire Format DetailsIt supports format 1 and format 2. If f
24、ormat 1 is selected, both master and slave drive data at SSI_CLK falling edge and sample data at the rising edge. If format 2 is selected, master drive and sample data at SSI_CLK falling edge, slave drive and sample data at SSI_CLK rising edge.SSI_CLK goes high midway through the comma nd' s mos
25、t sig ni fica nt bit (or LSB) and continues totoggle at the bit rate. One bit clock (format 1) or half one bit clock (format 2) period after the last comma nd bit, the external slave must return the serial data requested, with most sig ni fica nt bit first (or LSB first) on SSI_DR. SSI_CE_ / SSI_CE2
26、 deasserts high half clock (SSI_CLK) period (and 1/2/3 additional clock periods) later. Format 1 support back-to-back transfer, the start and end of back-to-back tran sfers are similar to those of a sin gle tran sfer. However, SSI_CE_ / SSI_CE2 remai ns asserted throughout the tran sfer. The end of
27、a character data on SSI_DR is immediately followed by the start of the next comma nd byte on SSI_DT.Jz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceJz4755 Multimedia Applicati
28、on Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceSSI_CLKSSI_CE_ SSI_DT SSI DRFigure 23-8 Natio nal Microwire Format 1 Si ngle TransferJz4755 Multimedia Application Processor Programming Manual, Revision
29、1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial Interface君正I IngenlcJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceJz4755 Multi
30、media Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceFigure 23-9 Nati onal Microwire Format 1 Back-to-back Tran sferSSI_CLKSSI_CE_ SSI_DTSSI DR1 -16-bit-MSB：<.LSB_ -I I1iiI!si Icomma nd2 -
31、17-bit dataMSB ?<：LSBJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Se
32、miconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceFigure 23-10 National Microwire Format 2 Read TimingSSI_CLKSSI_CE_SSI_DTSSI DRJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchro
33、nous Serial InterfaceJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceFigure 23-11 Natio nal Microwire Format 2 Write Timi ng23.6 In terrupt Operati onJz4755 Multimedia Applica
34、tion Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial InterfaceJz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.Synchronous Serial Interface503Jz4755 Multimedia Application Processor Programming Manual, Revision 1.0Copyright? 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.