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1、cordic算法verilog实现（复杂版）module cordic (clk,rst_n,ena,phase_in,sin_out,cos_out,eps);parameter DATA_WIDTH=8;parameter PIPELINE=8;input clk;input rst_n;input ena;inputDATA_WIDTH-1:0 phase_in;output DATA_WIDTH-1:0sin_out; output DATA_WIDTH-1:0cos_out;output DATA_WIDTH-1:0eps;reg DATA_WIDTH-1:0sin_out;reg
2、DATA_WIDTH-1:0cos_out;reg DATA_WIDTH-1:0eps;reg DATA_WIDTH-1:0phase_in_reg;reg DATA_WIDTH-1:0 x0,y0,z0;reg DATA_WIDTH-1:0x1,y1,z1;reg DATA_WIDTH-1:0x2,y2,z2;reg DATA_WIDTH-1:0x3,y3,z3;reg DATA_WIDTH-1:0x4,y4,z4;reg DATA_WIDTH-1:0x5,y5,z5;reg DATA_WIDTH-1:0x6,y6,z6;reg DATA_WIDTH-1:0x7,y7,z7;reg 1:0
3、quadrantPIPELINE:0;integer i;/get real quadrant and map to first_n quadrantalways(posedge clk or negedge rst_n)begin if(!rst_n) phase_in_reg=8b0000_0000; else if(ena) begin case(phase_in7:6) 2b00:phase_in_reg=phase_in; 2b01:phase_in_reg=phase_in-8h40;/-pi/2 2b10:phase_in_reg=phase_in-8h80;/-pi 2b11:
4、phase_in_reg=phase_in-8hc0;/-3pi/2 default:; endcase endendalways(posedge clk or negedge rst_n)begin if(!rst_n) begin x0=8b0000_0000; y0=8b0000_0000; z0=8b0000_0000; end else if(ena) begin x0=8h4D;/define aggregate constant Xi=1/P=1/1.6467=0.60725 (Xi=2*P+8h4D) y0=8h00; z0=phase_in_reg; endend/level 1always(posedge clk or negedge rst_n)begin if(!rst_n) begin x1=8b0000_0000; y1=8b0000_0000; z1=8b0000_0000; end else if(ena) if(z07=1b0) begin x1=x0-y0; y1=y0+x0;