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1、Xilinx中ise原语的使用1、IBUFGDS输入全局时钟及DCM分频使用：IBUFGDS #(.DIFF_TERM(FALSE), / DifferenTIal TerminaTIon (Virtex-4/5, Spartan-3E/3A).IOSTANDARD(DEFAULT) / Specifies the I/O standard for this buffer) IBUFGDS_inst (.O(CLK_SYS), / Clock buffer output.I(CLKP_SYS), / Diff_p clock buffer input.IB(CLKN_SYS) / Diff_n
2、 clock buffer input);DCM_BASE #(.CLKDV_DIVIDE(2.0), / Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5/ 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0.CLKFX_DIVIDE(3), / Can be any integer from 1 to 32.CLKFX_MULTIPLY(2), / Can be any integer from 2 to 32.CLKIN_DIVIDE_BY_2(FALSE), / TRUE
3、/FALSE to enable CLKIN divide by two feature.CLKIN_PERIOD(8.14),/(10.0), / Specify period of input clock in ns from 1.25 to 1000.00.CLKOUT_PHASE_SHIFT(NONE), / Specify phase shift mode of NONE or FIXED.CLK_FEEDBACK(1X), / Specify clock feedback of NONE, 1X or 2X.DCM_PERFORMANCE_MODE(MAX_SPEED), / Ca
4、n be MAX_SPEED or MAX_RANGE.DESKEW_ADJUST(SYSTEM_SYNCHRONOUS), / SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or/ an integer from 0 to 15.DFS_FREQUENCY_MODE(LOW), / LOW or HIGH frequency mode for frequency synthesis.DLL_FREQUENCY_MODE(LOW), / LOW, HIGH, or HIGH_SER frequency mode for DLL.DUTY_CYCLE_CORREC
5、TION(TRUE), / Duty cycle correction, TRUE or FALSE.FACTORY_JF(16hf0f0), / FACTORY JF value suggested to be set to 16hf0f0.PHASE_SHIFT(0), / Amount of fixed phase shift from -255 to 1023.STARTUP_WAIT(FALSE) / Delay configuration DONE until DCM LOCK, TRUE/FALSE) DCM_BASE_inst (.CLK0(CLK0), / 0 degree
6、DCM CLK output.CLK180(CLK180), / 180 degree DCM CLK output.CLK270(CLK270), / 270 degree DCM CLK output.CLK2X(CLK2X), / 2X DCM CLK output.CLK2X180(CLK2X180), / 2X, 180 degree DCM CLK out.CLK90(CLK90), / 90 degree DCM CLK output.CLKDV(clk4608), / Divided DCM CLK out (CLKDV_DIVIDE).CLKFX(clk), / DCM CL
7、K synthesis out (M/D).CLKFX180(CLKFX180), / 180 degree CLK synthesis out.LOCKED(LOCKED), / DCM LOCK status output.CLKFB(CLK0), / DCM clock feedback.CLKIN(CLK_SYS), / Clock input (from IBUFG, BUFG or DCM).RST(1b0) / DCM asynchronous reset input);2、ODDR、IDDR单边缘与双边缘触发的转换。单边缘输入双边缘输出：ODDR #(.DDR_CLK_EDGE
8、(OPPOSITE_EDGE), / OPPOSITE_EDGE or SAME_EDGE.INIT(1b0), / Initial value of Q: 1b0 or 1b1.SRTYPE(SYNC) / Set/Reset type: SYNC or ASYNC) ODDR_inst0 (.Q(DataOut0), / 1-bit DDR output.C(Clk), / 1-bit clock input.CE(CE), / 1-bit clock enable input.D1(DataIn0), / 1-bit data input (positive edge).D2(DataI
9、n8), / 1-bit data input (negative edge).R(Reset), / 1-bit reset.S(Set) / 1-bit set);双边缘输入，单边缘输出：IDDR #(.DDR_CLK_EDGE(OPPOSITE_EDGE), / OPPOSITE_EDGE, SAME_EDGE/ or SAME_EDGE_PIPELINED.INIT_Q1(1b0), / Initial value of Q1: 1b0 or 1b1.INIT_Q2(1b0), / Initial value of Q2: 1b0 or 1b1.SRTYPE(SYNC) / Set/Reset type: SYNC or ASYNC) IDDR_inst1 (.Q1(DataOutL1), / 1-bit output for positive edge of clock.Q2(DataOutH1), / 1-bit output for negative edge of clock.C(Clk), / 1-bit clock input.CE(CE), / 1-bit clock enable input.D(DataIn1), / 1-bit DDR data input.R(Reset), / 1-bit reset.S(Set) / 1-bit set);