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1、Data sheet acquired from Harris Semiconductor SCHS015 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to
2、 verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warr
3、ants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eac
4、h device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DE
5、SIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate de
6、sign and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right,
7、copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitut
8、e TIs approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated October 1987 Revised January 1999 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate 1999 Fairchild Semiconductor CorporationDS CD4001BC/CD4011BC Quad 2-Inp
9、ut NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits con- structed with N- and P-channel enhancement mode tran- sistors. They have equal source and sink current capa
10、bilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS. Features I Low power TTL: Fan out of 2 driving 74L compatib
11、ility:or 1 driving 74LS I 5V10V15V parametric ratings I Symmetrical output characteristics I Maximum input leakage 1 A at 15V over full temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin A
12、ssignments for DIP, SOIC and SOP CD4001BC Top View Pin Assignments for DIP and SOIC CD4011BC Top View Order NumberPackage NumberPackage Description CD4001BCMM14A14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4001BCSJM14D14-Lead Small Outline Package (SOP), EIAJ TYPE I
13、I, 5.3mm Wide CD4001BCNN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4011BCMM14A14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4011BCNN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 2 CD4001BC/CD4011BC Schemati
14、c Diagrams CD4001BC 1/4 of device shown J = A + B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4011BC 1/4 of device shown J = A B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4001BC/CD4011BC Abso
15、lute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these
16、 limits. The Electrical Characteristics tables provide conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise speci- fied. DC Electrical Characteristics (Note 2) Note 3: IOL and IOH are tested one output at a time. AC Electrical Characteristics (No
17、te 4) CD4001BC: TA = 25C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/C. Note 4: AC Parameters are guaranteed by DC correlated testing. Voltage at any Pin0.5V to VDD +0.5V Power Dissipation (PD) Dual-In-Line700 mW Small Outline500 mW VDD Range0.5 VDC to +18 V
18、DC Storage Temperature (TS)65C to +150C Lead Temperature (TL) (Soldering, 10 seconds)260C Operating Range (VDD)3 VDC to 15 VDC Operating Temperature Range CD4001BC, CD4011BC40C to +85C SymbolParameterConditions 40C+25C+85C Units MinMaxMinTypMaxMinMax IDDQuiescent DeviceVDD = 5V, VIN = VDD or VSS10.0
19、0417.5A CurrentVDD = 10V, VIN = VDD or VSS20.005215A VDD = 15V, VIN = VDD or VSS40.006430A VOLLOW LevelVDD = 5V0.0500.050.05V Output VoltageVDD = 10V|IO| VDD/2 VOL 4.5V, VOL 4.5V, VOL 13.5V, VOL 13.5V, VOL 9V, VOL 9V, VOL VDD/2 VOL VDD/2 VOL 4.5V, VOL 4.5V, VOL 13.5V, VOL 13.5V, VOL 9V, VOL 9V, VOL
20、VDD/2 VOL 25C (calculated from RON values shown). No VDD current will flow through RL if the switch current flows into OUT/IN pin. Typical Performance Characteristics “ON” Resistance vs Signal Voltage for TA = 25C “ON” Resistance as a Function of Temperature for VDD VEE = 15V “ON” Resistance as a Fu
21、nction of Temperature for VDD VEE = 10V “ON” Resistance as a Function of Temperature for VDD VEE = 5V CD4051BC CD4052BC CD4053BC Switching Time Waveforms 10 CD4051BC CD4052BC CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JE
22、DEC MS-012, 0.150 Narrow Package Number M16A CD4051BC CD4052BC CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 12 CD4051BC CD4052BC CD4053BC Physical Dimensions inches (millimeters
23、) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demu
24、ltiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
25、Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICON
26、DUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeli
27、ng, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effe
28、ctiveness. 1 Data sheet acquired from Harris Semiconductor SCHS047C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright 1999, Texas Instruments Incorporated CD4051B, CD4052B, CD4053B CMOS Analog Multiplexers/Demultiplexers with Logic Leve
29、l Conversion The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, a VDD-VEEof up to
30、 13V can be controlled; for VDD-VEElevel differences above 13V, a VDD-VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE= -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low qui
31、escent power over the full VDD-VSS and VDD-VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C,
32、 and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs
33、 of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-
34、throw confi guration. When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. Features Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20
35、V - Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P Low ON Resistance, 125 (Typ) Over 15VP-PSignal Input Range for VDD-VEE = 18V High OFF Resistance, Channel Leakage of 100pA (Typ) at VDD-VEE = 18V Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD-VSS
36、 = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V) Matched Switch Characteristics, rON = 5 (Typ) for VDD-VEE = 15V Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2W (Typ) at VDD-VSS = VDD-VEE = 10V Binary Address Decoding on Chip 5V, 10V
37、and 15V Parametric Ratings 10% Tested for Quiescent Current at 20V Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC Break-Before-Make Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and Demultiplexing A/D and D/A Conversi
38、on Signal Gating Ordering Information PART NUMBER TEMP. RANGE (oC)PACKAGE PKG. NO. CD4051BF, CD4052BF, CD4053BF -55 to 12516 Ld CERDIP F16.3 CD4051BE, CD4052BE, CD4053BE -55 to 12516 Ld PDIPE16.3 CD4051BM-55 to 12516 Ld SOICM16.15 August 1998 - Revised August 1999 /Title (CD405 1B, CD4052 B, CD4053
39、B) /Sub- ject (CMOS Analog Multi- plex- ers/Dem ultiplex- ers with Logic Level Conver- sion) /Author () /Key- words (Harris Semi- conduc- tor, CD4000 2 Pinouts CD4051B (PDIP, CERDIP, SOIC) TOP VIEW CD4052B (PDIP, CERDIP, SOIC) TOP VIEW CD4053B (PDIP, CERDIP) TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5
40、 7 6 8 4 6 COM OUT/IN 7 5 INH VSS VEE VDD 1 0 3 A B C 2 CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 0 2 COMMON “Y” OUT/IN 3 1 INH VSS VEE VDD 1 COMMON “X” OUT/IN 0 3 A B 2 Y CHANNELS IN/OUT Y CHANNELS IN/OUT X CHANNELS IN/OUT X CHANNELS IN/OUT 14 15 16 9 13
41、 12 11 10 1 2 3 4 5 7 6 8 by bx cy OUT/IN CX OR CY IN/OUT CX INH VSS VEE VDD OUT/IN ax OR ay ay ax A B C OUT/IN bx OR by IN/OUT IN/OUT Functional Block Diagrams CD4051B 11 10 9 6 A B C INH 134251121514 TG TG TG TG TG TG TG TG 3 COMMON OUT/IN 01234567 BINARY TO 1 OF 8 DECODER WITH INHIBIT LOGIC LEVEL
42、 CONVERSION 87VSSVEE 16 V DD CHANNEL IN/OUT All inputs are protected by standard CMOS protection network. CD4051B, CD4052B, CD4053B 3 CD4052B CD4053B Functional Block Diagrams (Continued) 12111514 0123 3210 X CHANNELS IN/OUT Y CHANNELS IN/OUT BINARY TO 1 OF 4 DECODER WITH INHIBIT 13 3 COMMON Y OUT/I
43、N COMMON X OUT/IN 78 16 6 9 10 A B INH VSSVEE VDD TG TG TG TG TG TG TG TG 4251 LOGIC LEVEL CONVERSION 11 10 9 6 A B C INH 12351213 TG TG TG TG TG TG 4 COMMON OUT/IN axaybxbycxcy 8 7VSSVEE 16 V DD IN/OUT 15 14 BINARY TO 1 OF 2 DECODERS WITH INHIBIT LOGIC LEVEL CONVERSION VDD All inputs are protected
44、by standard CMOS protection network. COMMON OUT/IN COMMON OUT/IN ax OR ay bx OR by cx OR cy CD4051B, CD4052B, CD4053B 4 TRUTH TABLES INPUT STATES “ON” CHANNEL(S)INHIBITCBA CD4051B 00000 00011 00102 00113 01004 01015 01106 01117 1XXXNone CD4052B INHIBITBA 0000x, 0y 0011x, 1y 0102x, 2y 0113x, 3y 1XXNo
45、ne CD4053B INHIBITA OR B OR C 00ax or bx or cx 01ay or by or cy 1XNone X = Dont Care CD4051B, CD4052B, CD4053B 5 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-) Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V DC Input Voltage Range . . . . . . . . . . .
46、. . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . 10mA Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Thermal Resistance (Typical, Note 1)JA (oC/W)JC (oC/W) PDIP Package . . . . . . . .
47、. . . . . . . . . . .78N/A CERDIP Package. . . . . . . . . . . . . . . . . 11545 SOIC Package . . . . . . . . . . . . . . . . . . . 113N/A Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Tempera
48、ture Range. . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifi cationsCommon Conditio