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1、HCC/HCF40100B 32-STAGESTATIC LEFT/RIGHT SHIFT REGISTER DESCRIPTION .FULLY STATIC OPERATION .SHIFT LEFT/SHIFT RIGHT CAPABILITY .MULTIPLEPACKAGE CASCADING .RECIRCULATE CAPABILITY .LIFO OR FIFO CAPABILITY .STANDARDIZEDSYMMETRICALOUTPUT CHARACTERISTICS .QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE
2、.5V, 10V, AND 15V PARAMETRIC RATINGS .INPUT CURRENTOF100nA AT18V AND 25C FOR HCC DEVICE .100% TESTEDFOR QUIESCENTCURRENT .MEETSALLREQUIREMENTSOFJEDECTEN- TATIVE STANDARD No. 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIESCMOS DEVICES” June 1989 The HCC40100B (extended temperature range)
3、and HCF40100B (intermediate temperature range) are monolithic integrated circuits, available in 16- lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF40100B is a 32-stage shift register containing 32D-typemaster- slave flip-flops. The data present at the SHIFT- RIGHT
4、 INPUT is transferred into the first register stagesynchronously withthepositive CLOCKedge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROLis also hig
5、h, dataat the SHIFT-LEFT INPUTistransferred into the32ndreg- ister stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBITis low. The state of the LEFT/RIGHT CONTROL, RECIRCU- LATE CONTROL,and CLOCK INHIBIT should not bechanged whentheCLOCKishigh. Dataisshifted one stage l
6、eft or one stage right depending on the state of the LEFT/RIGHT CONTROL, synchron- ously with the positive CLOCK edge. Data clocked intothefirstor32ndregister statesisavailable atthe SHIFT-LEFT or SHIFT-RIGHT OUTPUT respec- tively, on the next negative CLOCK transition (see DataTransfer Table). No s
7、hiftingoccurs on the posi- tive CLOCKedge if the CLOCK INHIBITline is at a highlevel. WiththeRECIRCULATECONTROLlow, EY (Plastic Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC40100BFHCF40100BM1 HCF40100BEYHCF40100BC1 PIN CONNECTIONS data in the 32nd stage is shifted into the first stage when th
8、e LEFT/RIGHTCONTROL is low and from the1st stage to the 32nd stage when the LEFT/RIGHT CONTROL ishigh. M1 (Micro Package) F (Ceramic FritSeal Package) 1/13 FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS SymbolParameterValueUnit VDD*Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 V V ViInput
9、 Voltage 0.5 to VDD+ 0.5V IIDC Input Current (any one input) 10mA PtotTotal Power Dissipation (per package) Dissipation per Output Transistor for Top= Full Package-temperature Range 200 100 mW mW TopOperating Temperature : HCC Types HCF Types 55 to + 125 40 to + 85 C C TstgStorage Temperature 65 to
10、+ 150C RECOMMENDED OPERATING CONDITIONS SymbolParameterValueUnit VDDSupply Voltage : HCC Types HCF Types 3 to + 18 3 to + 15 V V VIInput Voltage0 to VDDV TopOperating Temperature : HCC Types HCF Types 55 to + 125 40 to + 85 C C Stresses above those listed under ”Absolute Maximum Ratings” may cause p
11、ermanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect
12、 device reliability. HCC/HCF40100B 2/13 LOGIC DIAGRAM HCC/HCF40100B 3/13 CONTROL Left/Right Control Clock Inhibit Recirculate Control ActionInput Bit Origin 101Shift LeftShift Left Input 100Shift LeftStage 1 001Shift RightShift Right Input 000Shift RightStage 32 X1XNo Shift 0 = Lowlevel1 =High level
13、X= Dont Care.NC =No change. * For Shift-Right ModeFor Shift-left Mode Data Input =SHIFT-RIGHT INPUT (Pin 11)Data input =SHIFT LEFT INPUT (Pin 6) Internal Stage = Stage 1 (Q1)Internal Stage = Stage 32 (Q32) Output =SHIFT-LEFT OUTPUT (Pin 4).Output = SHIFT-RIGHT OUTPUT (Pin 12). TRUTH TABLES DATA TRAN
14、SFER Initial StateClockResulting State Data InputClock InhibitInternal StageLevel Change Internal Stage Q Output 00X / 0NC X00 NC0 10X / 1NC X01 NC1 X11XNCNC STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Test ConditionsValue VIVO|IO|VD DTLow*25CTHigh* SymbolParameter (V)(
15、V)(A)(V) Min.Max.Min.Typ.Max.Min.Max. Unit ILQuiescent Current HCC Types 0/ 5550.045150 A 0/1010100.0410300 0/1515200.0420600 0/20201000.081003000 HCF Types 0/ 55200.0420150 0/1010400.0440300 0/1515800.0480600 VOHOutput High Voltage 0/ 5 B01A B 00A B11A B 1 = HIGH LEVEL 0 = LOW LEVEL HCC/HCF40181B 3
16、/12 LOGIC DIAGRAM Active-low Data HCC/HCF40181B 4/12 STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Test ConditionsValue VIVO|IO|VD DTLow*25CTHigh* SymbolParameter (V)(V)(A)(V) Min.Max.Min.Typ.Max.Min.Max. Unit ILQuiescent Current HCC Types 0/ 5550.045150 A 0/1010100.04103
17、00 0/1515200.0420600 0/20201000.081003000 HCF Types 0/ 55200.0420150 0/1010400.0440300 0/1515800.0480600 VOHOutput High Voltage 0/ 5 10 K and 2 RTC INPUT EQUIVALENT CIRCUITPIN DESCRIPTION RC OSCILLATOR CIRCUIT PIN NoSYMBOLNAME AND FUNCTION 12, 13A, BTime Select Input 4, 11NCNot Connected 1, 2 RTC, C
18、TC External Resistor, Capaci- tor Connection 3RS External Resistor Con- nection or External Clock Input 5ARAuto Reset Input 6MRMaster Reset Input 10MODEMode Select Input 9 Q/Q SELECT Output Selector 8QOutput 7VSSNegative Supply Voltage 14VDDPositive Supply Voltage HCF4541B 3/10 FUNCTIONAL DIAGRAM FR
19、EQUENCY SELECTION TABLETRUTH TABLE LOGIC DIAGRAM ABN. of Stages N Count 2N LL138192 LH101024 HL18256 HH1665536 PIN STATE LH 5Auto Reset OnAuto Reset Disable 6Master Reset OffMaster Reset On 9 Output Initially Low After Reset (Q) Output Initially High After Reset (Q) 10Single Transition ModeRecycle M
20、ode HCF4541B 4/10 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSSpin voltage. RECOMMENDED OPERATING CONDITIONS SymbolParameterValueUnit V
21、DDSupply Voltage-0.5 to +22V VIDC Input Voltage-0.5 to VDD+ 0.5V IIDC Input Current 10mA PDPower Dissipation per Package200mW Power Dissipation per Output Transistor100mW TopOperating Temperature-55 to +125C TstgStorage Temperature-65 to +150C SymbolParameterValueUnit VDDSupply Voltage 3 to 20V VIIn
22、put Voltage0 to VDDV TopOperating Temperature-55 to 125C HCF4541B 5/10 DC SPECIFICATIONS The Noise Margin for both ”1” and ”0” level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V SymbolParameter Test ConditionValue Unit VI (V) VO (V) |IO| (A) VDD (V) TA= 25C-40 to 85C-55 to 1
23、25C Min.Typ.Max.Min.Max.Min.Max. ILQuiescent Current0/550.045150150 A 0/10100.0410300300 0/15150.0420600600 0/20200.0810030003000 VOHHigh Level Output Voltage 0/5 B) and three cascading inputs (A B) that permit systems designers to expand the com- parator function to 8, 12, 16 . 4 N bits. When a sin
24、gle HCC/HCF4585B is used, the cascading in- puts are connected as follows : (A B)= high.Cascadingthese units for comparison of more than 4 bits is accomplished as shownin typical application. EY (Plastic Package) F (Ceramic Frit SealPackage) C1 (Plastic Chip Carrier) ORDERCODES : HCC4585BFHCF4585BM1
25、 HCF4585BEYHCF4585BC1 PIN CONNECTIONS M1 (Micro Package) 1/12 ABSOLUTE MAXIMUM RATINGS SymbolParameterValueUnit VDD*Supply Voltage :HCC Types HCF Types 0.5 to + 20 0.5 to + 18 V V ViInput Voltage 0.5 to VDD+ 0.5V IIDC Input Current (any one input) 10mA PtotTotal Power Dissipation (per package) Dissi
26、pation per Output Transistor for Top= Full Package-temperature Range 200 100 mW mW TopOperating Temperature : HCC Types HCF Types 55 to + 125 40 to + 85 C C TstgStorage Temperature 65 to + 150C Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. Thi
27、s is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltages
28、are with respect to VSS(GND). FUNCTIONAL DIAGRAM RECOMMENDED OPERATING CONDITIONS SymbolParameterValueUnit VDDSupply Voltage : HCC Types HCF Types 3 to 18 3 to 15 V V VIInput Voltage0 to VDDV TopOperating Temperature : HCC Types HCF Types 55 to + 125 40 to + 85 C C HCC/HCF4585B 2/12 LOGIC DIAGRAM In
29、puts ComparingCascading Outputs A 3, B3A2, B2A1, B1A0, B0A BA B A3 B3 A3 = B3 A3 = B3 A3 = B3 X A2 B2 A2 = B2 A2 = B2 X X A1 B1 A1 = B1 X X X A0 B0 X X X X X X X X 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 A3 = B3 A3 = B3 A3 = B3 A2 = B2 A2 = B2 A2 = B2 A1 = B1 A1 = B1 A1 = B1 A0 = B0 A0 = B0 A0 = B0 0 0 1 0
30、1 0 1 X X 0 0 1 0 1 0 1 0 0 A3 = B3 A3 = B3 A3 = B3 A3 1 k) then it is necessary to incorporate a capacitor C of such value that: , otherwise oscillation can occur on the edges of a pulse. Cpis the external parasitic capacitance between input and output; the value depends on the circuit board layout
31、. Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb= 25 C. Fig.10 Schmitt trigger driven via a high impedance (R 1 k). C Cp - - VDDVSS VH - - January 19957 Philips Semiconductors Product specifi cation Hex inverting Schmitt trigger HEF40106B gates APPLICATION INFORMATION Some
32、examples of applications for the HEF40106B are: Wave and pulse shapers Astable multivibrators Monostable multivibrators. Fig.11 The HEF40106B used as an astable multivibrator. DATA SHEETDATA SHEET Product specifi cation File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4011B g
33、ates Quadruple 2-input NAND gate For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC January 19952 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate H
34、EF4011B gates DESCRIPTION The HEF4011B provides the positive quadruple 2-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.1 Functional diagram. HEF4011BP(N):14-lead DIL; plastic (SOT27-1) HEF4011BD(F):14-lead DIL; ceram
35、ic (cerdip) (SOT73) HEF4011BT(D):14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDDLIMITS category GATES See Family Specifications Fig.3 Logic diagram (one gate). January 19953 Philips Semiconductors Product specifi cation Quadruple 2-input N
36、AND gate HEF4011B gates AC CHARACTERISTICS VSS= 0 V; Tamb= 25 C; CL= 50 pF; input transition times 20 ns VDD V SYMBOLTYPMAX TYPICAL EXTRAPOLATION FORMULA Propagation delays555110ns28 ns+(0,55 ns/pF) CL In On10tPHL; tPLH2545ns14 ns+(0,23 ns/pF) CL 152035ns12 ns+(0,16 ns/pF) CL Output transition times
37、560120ns10 ns+(1,0 ns/pF) CL HIGH to LOW10tTHL3060ns9 ns+(0,42 ns/pF) CL 152040ns6 ns+(0,28 ns/pF) CL 560120ns10 ns+(1,0 ns/pF) CL LOW to HIGH10tTLH3060ns9 ns+(0,42 ns/pF) CL 152040ns6 ns+(0,28 ns/pF) CL VDD V TYPICAL FORMULA FOR P (W) Dynamic power51300 fi+ (foCL) VDD2where dissipation per106000 fi
38、+ (foCL) VDD2fi= input freq. (MHz) package (P)1520 100 fi+ (foCL) VDD2fo= output freq. (MHz) CL= load capacitance (pF) (foCL) = sum of outputs VDD= supply voltage (V) DATA SHEETDATA SHEET Product specifi cation File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4011UB gates Qua
39、druple 2-input NAND gate For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC January 19952 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate HEF4011UB
40、 gates DESCRIPTION The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. Fig.1 Functional diagram.
41、 HEF4011UBP(N):14-lead DIL; plastic (SOT27-1) HEF4011UBD(F):14-lead DIL; ceramic (cerdip) (SOT73) HEF4011UBT(D):14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDDLIMITS category GATES See Family Specifications for VIH/VILunbuffered stages Fig
42、.3Schematic diagram (one gate). The splitting-up of the n-transistors provide identical inputs. January 19953 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate HEF4011UB gates AC CHARACTERISTICS VSS= 0 V; Tamb= 25 C; CL= 50 pF; input transition times 20 ns VDD V SYMBOLTYP.MAX
43、. TYPICAL EXTRAPOLATION FORMULA Propagation delays In On560120ns25 ns+(0,70 ns/pF) CL HIGH to LOW10tPHL2550ns12 ns+(0,27 ns/pF) CL 152040ns10 ns+(0,20 ns/pF) CL 53570ns8 ns+(0,55 ns/pF) CL LOW to HIGH10tPLH2040ns9 ns+(0,23 ns/pF) CL 151735ns9 ns+(0,16 ns/pF) CL Output transition575150ns15 ns+(1,20 n
44、s/pF) CL times10tTHL3060ns6 ns+(0,48 ns/pF) CL HIGH to LOW152040ns4 ns+(0,32 ns/pF) CL 560110ns10 ns+(1,00 ns/pF) CL LOW to HIGH10tTLH3060ns9 ns+(0,42 ns/pF) CL 152040ns6 ns+(0,28 ns/pF) CL Input capacitanceCIN10pF VDD V TYPICAL FORMULA FOR P (W) Dynamic power5500 fi+ (foCL) VDD2where dissipation pe
45、r105 000 fi+ (foCL) VDD2fi= input freq. (MHz) package (P)1525 000 fi+ (foCL) VDD2fo= output freq. (MHz) CL= load capacitance (pF) (foCL) = sum of outputs VDD= supply voltage (V) January 19954 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate HEF4011UB gates Fig.4Typical trans
46、fer characteristics; one input, the other input connected to VDD; VO; ID(drain current); IO= 0; VDD= 5 V. Fig.5Typical transfer characteristics; one input, the other input connected to VDD; VO; ID(drain current); IO= 0; VDD= 10 V. Fig.6Typical transfer characteristics; one input, the other input con
47、nected to VDD; VO; ID(drain current); IO= 0; VDD= 15 V. January 19955 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate HEF4011UB gates Fig.7 Test set-up for measuring forward transconductance gfs= dio/dviat vois constant (see also graph Fig.8). Fig.8 Typical forward transcon
48、ductance gfsas a function of the supply voltage at Tamb= 25 C. A : average, B : average + 2 s, C : average 2 s, where s is the observed standard deviation. January 19956 Philips Semiconductors Product specifi cation Quadruple 2-input NAND gate HEF4011UB gates APPLICATION INFORMATION Some examples of
49、 applications for the HEF4011UB are shown below. Because of the fact that this circuit is unbuffered, it is suitable for use in (partly) analogue circuits. Fig.9(a) Astable relaxation oscillator using two HEF4011UB gates; the diodes may be BAW62; C2 is a parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram. INHO LH HOSC In Fig.9 the oscillation frequency i