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1、EE141 1 Digital Integrated Circuits2nd Combinational Circuits Digital Integrated Digital Integrated CircuitsCircuits A Design PerspectiveA Design Perspective Designing CombinationalDesigning Combinational Logic CircuitsLogic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikoli November 2002.
2、EE141 2 Digital Integrated Circuits2nd Combinational Circuits Combinational vs. Sequential LogicCombinational vs. Sequential Logic Combinational Sequential Output = f(In)Output = f(In, Previous In) Combinational Logic Circuit OutIn Combinational Logic Circuit Out In State EE141 3 Digital Integrated
3、Circuits2nd Combinational Circuits Static CMOS CircuitStatic CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, imple
4、mented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. EE141 4 Digital Integrated Circuits2nd Combinational
5、Circuits Static Complementary CMOSStatic Complementary CMOS VDD F(In1,In2,InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks EE141 5 Digital Integrated Circuits2nd Combinational Circuits NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Serie
6、s/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high XY AB Y = X if A and B X Y A B Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1 EE141 6 Digital Integrated Circuits2nd Combinational Circui
7、ts PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection X Y AB Y = X if A AND B = A + B X Y A B Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 PMOS switch closes when switch control input is low EE141 7 Digital Integrated Circuits2nd Co
8、mbinational Circuits Threshold DropsThreshold Drops VDD VDD 0PDN 0 VDD CL CL PUN VDD 0 VDD - VTn CL VDD VDD VDD |VTp| CL S DS D VGS S SD D VGS EE141 8 Digital Integrated Circuits2nd Combinational Circuits Complementary CMOS Logic StyleComplementary CMOS Logic Style EE141 9 Digital Integrated Circuit
9、s2nd Combinational Circuits Example Gate: NANDExample Gate: NAND EE141 10 Digital Integrated Circuits2nd Combinational Circuits Example Gate: NORExample Gate: NOR EE141 11 Digital Integrated Circuits2nd Combinational Circuits Complex CMOS GateComplex CMOS Gate OUT = D + A (B + C) D A BC D A B C EE14
10、1 12 Digital Integrated Circuits2nd Combinational Circuits Constructing a Complex GateConstructing a Complex Gate C (a) pull-down network SN1 SN4 SN2 SN3 D F F A D B C D F A B C (b) Deriving the pull-up network hierarchically by identifying sub-nets D A A B C VDDVDD B (c) complete gate EE141 13 Digi
11、tal Integrated Circuits2nd Combinational Circuits Cell DesignCell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width EE141 14 Digital Integrated
12、Circuits2nd Combinational Circuits Standard Cell Layout Methodology Standard Cell Layout Methodology 1980s1980s signals Routing channel VDD GND EE141 15 Digital Integrated Circuits2nd Combinational Circuits Standard Cell Layout Methodology Standard Cell Layout Methodology 1990s1990s M2 No Routing ch
13、annels VDD GND M3 VDD GND Mirrored Cell Mirrored Cell EE141 16 Digital Integrated Circuits2nd Combinational Circuits Standard CellsStandard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rail
14、s 10 In Out VDD GND EE141 17 Digital Integrated Circuits2nd Combinational Circuits Standard CellsStandard Cells In Out VDD GND InOut VDD GND With silicided diffusion With minimal diffusion routing OutIn VDD M2 M1 EE141 18 Digital Integrated Circuits2nd Combinational Circuits Standard CellsStandard C
15、ells A Out VDD GND B 2-input NAND gate B VDD A EE141 19 Digital Integrated Circuits2nd Combinational Circuits Stick DiagramsStick Diagrams Contains no dimensions Represents relative positions of transistors In Out VDD GND Inverter A Out VDD GND B NAND2 EE141 20 Digital Integrated Circuits2nd Combina
16、tional Circuits Stick DiagramsStick Diagrams C AB X = C (A + B) B A C i j j VDD X X i GND AB C PUN PDN A B C Logic Graph EE141 21 Digital Integrated Circuits2nd Combinational Circuits Two Versions of C Two Versions of C (A + B) (A + B) X CABABC X VDD GND VDD GND EE141 22 Digital Integrated Circuits2
17、nd Combinational Circuits Consistent Euler PathConsistent Euler Path j VDD X X i GND AB C ABC EE141 23 Digital Integrated Circuits2nd Combinational Circuits OAI22 Logic GraphOAI22 Logic Graph C AB X = (A+B)(C+D) B A D VDD X X GND AB C PUN PDN C D D A B C D EE141 24 Digital Integrated Circuits2nd Com
18、binational Circuits Example: x = Example: x = abab+ +cdcd GND x a b c d VDD x GND x a b c d VDD x (a) Logic graphs for (ab+cd) (b) Euler Paths a b c d acd x VDD GND (c) stick diagram for ordering a b c d b EE141 25 Digital Integrated Circuits2nd Combinational Circuits Multi-Fingered TransistorsMulti
19、-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance EE141 26 Digital Integrated Circuits2nd Combinational Circuits Properties of Complementary CMOS Gates Properties of Complementary CMOS Gates SnapshotSnapshot High noise margins: VOH and VOL are at VDD and GND, respectiv
20、ely. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions) EE141 27 Digital Integrated Circuits2nd Combinational Circuits CMOS PropertiesCMOS Properties Full rail-to-rail swi
21、ng; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power
22、dissipation Propagation delay function of load capacitance and resistance of transistors EE141 28 Digital Integrated Circuits2nd Combinational Circuits Switch Delay ModelSwitch Delay Model A Req A Rp A Rp A Rn CL A CL B Rn A Rp B Rp A Rn Cint B Rp A Rp A Rn B Rn CL Cint NAND2 INV NOR2 EE141 29 Digit
23、al Integrated Circuits2nd Combinational Circuits Input Pattern Effects on DelayInput Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 Rp/2 CL one input goes low delay is 0.69 Rp CL High to low transition both inputs go high
24、delay is 0.69 2Rn CL CL B Rn A Rp B Rp A Rn Cint EE141 30 Digital Integrated Circuits2nd Combinational Circuits Delay Dependence on Input PatternsDelay Dependence on Input Patterns -0.5 0 0.5 1 1.5 2 2.5 3 0100200300400 A=B=10 A=1, B=10 A=1 0, B=1 time ps Voltage V 81A= 10, B=1 80A=1, B=10 45A=B=10
25、61A= 01, B=1 64A=1, B=01 67A=B=01 Delay (psec) Input Data Pattern NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF EE141 31 Digital Integrated Circuits2nd Combinational Circuits Transistor SizingTransistor Sizing CL B Rn A Rp B Rp A Rn Cint B Rp A Rp A Rn B Rn CL Cint 2 2 22 1 1 4 4 EE141 32 Digit
26、al Integrated Circuits2nd Combinational Circuits Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate OUT = D + A (B + C) D A BC D A B C 1 2 22 4 4 8 8 6 3 6 6 EE141 33 Digital Integrated Circuits2nd Combinational Circuits Fan-In ConsiderationsFan-In Considerations DCBA D C B A
27、 CL C3 C2 C1 Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case. EE141 34 Digital Integrated Circuits2nd Combinational Circuits t tp p as a Function of Fan-In as a Function of Fan-In tpLH
28、 tp (psec) fan-in Gates with a fan-in greater than 4 should be avoided. 0 250 500 750 1000 1250 246810121416 tpHL quadratic linear tp EE141 35 Digital Integrated Circuits2nd Combinational Circuits t tp p as a Function of Fan-Out as a Function of Fan-Out 246810121416 tpNOR2 tp (psec) eff. fan-out All
29、 gates have the same drive current. tpNAND2 tpINV Slope is a function of “driving strength” EE141 36 Digital Integrated Circuits2nd Combinational Circuits t tp p as a Function of Fan-In and Fan-Out as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan
30、-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO EE141 37 Digital Integrated Circuits2nd Combinational Circuits Fast Complex Gates:Fast Complex Gates: Design Technique 1Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressi
31、ve sizing InN CL C3 C2 C1 In1 In2 In3 M1 M2 M3 MN Distributed RC line M1 M2 M3 MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks EE141 38 Digital Integrated Circuits2nd Combinational Circuits Fast Complex Gates:Fast Complex G
32、ates: Design Technique 2Design Technique 2 Transistor ordering C2 C1 In1 In2 In3 M1 M2 M3CL C2 C1 In3 In2 In1 M1 M2 M3CL critical pathcritical path charged 1 01 charged charged 1 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL 1 1 01 charged discharged di
33、scharged EE141 39 Digital Integrated Circuits2nd Combinational Circuits Fast Complex Gates:Fast Complex Gates: Design Technique 3Design Technique 3 Alternative logic structures F = ABCDEFGH EE141 40 Digital Integrated Circuits2nd Combinational Circuits Fast Complex Gates:Fast Complex Gates: Design T
34、echnique 4Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL CL EE141 41 Digital Integrated Circuits2nd Combinational Circuits Fast Complex Gates:Fast Complex Gates: Design Technique 5Design Technique 5 Reducing the voltage swing linear reduction in delay also reduces power c
35、onsumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) EE141 42 Digital Integrated Circuits2nd Combinational Circuits Sizing Logic P
36、aths for SpeedSizing Logic Paths for Speed Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intels microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the invert
37、er chain can we generalize it for any type of logic? EE141 43 Digital Integrated Circuits2nd Combinational Circuits Buffer ExampleBuffer Example N i iii fgpDelay 1 For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci 4 How to generalize this to any logic path? CL InOut 12N (in units of inv) EE141 44 Di
38、gital Integrated Circuits2nd Combinational Circuits Logical EffortLogical Effort fgp C C CRkDelay in L unitunit 1 p intrinsic delay (3kRunitCunit) - gate parameter f(W) g logical effort (kRunitCunit) gate parameter f(W) f effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide
39、 everything by inv (everything is measured in unit delays inv) Assume = 1. EE141 45 Digital Integrated Circuits2nd Combinational Circuits Delay in a Logic GateDelay in a Logic Gate Gate delay: d = h + p effort delayintrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logi
40、cal effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size EE141 46 Digital Integrated Circuits2nd Combinational Circuits Logical EffortLogical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS
41、 gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity EE141 47 Digital Integrated Circuits2nd Combinational Circuits Logical EffortLogical Effort Logical effort
42、is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3g = 5/3 B A AB F VDDVDD AB A B F VDD A A F 1 222 2 2 11 4 4 Inverter2-input NAND2-input NOR EE141 48 Digital Integrated Circuits2nd Combinational Circuits Logical Effort of G
43、atesLogical Effort of Gates Fan-out (h) Normalized delay (d) t 1 23 4 5 6 7 pINV tpNAND F(Fan-in) g = p = d = g = p = d = EE141 49 Digital Integrated Circuits2nd Combinational Circuits Logical Effort of GatesLogical Effort of Gates Fan-out (h) Normalized delay (d) t 1 23 4 5 6 7 pINV tpNAND F(Fan-in
44、) g = 1 p = 1 d = h+1 g = 4/3 p = 2 d = (4/3)h+2 EE141 50 Digital Integrated Circuits2nd Combinational Circuits Logical Effort of GatesLogical Effort of Gates Intrinsic? Delay Effort Delay 12345 Fanout f 1 2 3 4 5 Inverter: g = 1; p = 1 2-input NAND: g = 4/3; p = 2 Normalized Delay EE141 51 Digital
45、Integrated Circuits2nd Combinational Circuits Add Branching EffortAdd Branching Effort Branching effort: pathon pathoffpathon C CC b EE141 52 Digital Integrated Circuits2nd Combinational Circuits Multistage NetworksMultistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path
46、 logical effort: G = g1g2gN Branching effort: B = b1b2bN Path effort: H = GFB Path delay D = di = pi + hi N i iii fgpDelay 1 EE141 53 Digital Integrated Circuits2nd Combinational Circuits Optimum Effort per StageOptimum Effort per Stage Hh N When each stage bears the same effort: N Hh PNHpfgD N iii
47、/1 Minimum path delay Effective fanout of each stage: ii ghf Stage efforts: g1f1 = g2f2 = = gNfN EE141 54 Digital Integrated Circuits2nd Combinational Circuits Optimal Number of StagesOptimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stag
48、es and optimal sizing inv N NpNHD /1 0ln /1/1/1 inv NNN pHHH N D N Hh /1 Substitute best stage effort EE141 55 Digital Integrated Circuits2nd Combinational Circuits Logical EffortLogical Effort From Sutherland, Sproull EE141 56 Digital Integrated Circuits2nd Combinational Circuits Example: Optimize PathExample: Optimize Path Effective fanout, F = G = H = h = a = b = 1 a b c 5 g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c EE141 57 Digital Integrated Circuits2nd Combinational Circuits Example: Optimize PathExamp