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1、972IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 51, NO. 3, MARCH 2003 Linearity Analysis of CMOS for RF Application Sanghoon Kang, Byounggi Choi, and Bumman Kim, Senior Member, IEEE AbstractThe linearity of CMOS has been analyzed using the Taylor series. Transconductance and output con
2、ductance are two dominant nonlinear sources of CMOS. At a low frequency, the transconductance is a dominant nonlinear source for a low load impedance, but for a usual operation level impedance the output conductance is a dominant nonlinear source. Capacitances and the substratenetworkdo notgeneratea
3、nysignificantnonlinearity, but theysuppressoutput-conductancenonlinearityatahighfrequency because output impedance is reduced by the capacitiveshunts, and output voltage swing is also reduced. Therefore, above 23 GHz, the transconductance becomes a dominant nonlinear source for a usualloadimpedance.
4、Ifthesecapacitiveelementsaretunedoutfor a power match, the behavior becomes similar to the low-frequency case. As gate length is reduced, the transconductance becomes more linear, but the output conductance becomes more nonlinear. At a low frequency, CMOS linearity is degraded as the gate length bec
5、omes shorter, but at a higher frequency (above 23 GHz), linearity can be improved. Index TermsCMOS, linearity. I. INTRODUCTION T HERE IS A strong interest in using CMOS technology for RF and microwave circuits. To support the growing needs of RF circuits, the various characteristics of CMOS have bee
6、n evaluated using various device models. However, they are usually small-signal behaviors, such as small-signal gain, noise figure, etc. More recently, the large signal characteristics of CMOS, such as power gain, power generation, efficiency, and mixer operation have been intensively studied. Howev
7、er, linearity is always one of the most important issues for RF circuit design. SomeresearchconsidersonlythetransconductanceinCMOS linearity analysis, while other effects are neglected 1. For a short gate CMOS, however, the output conductance becomes an important nonlinear source and must be include
8、d in CMOS analysis. Capacitances and substrate effects are also far from negligible at high frequency. We have studied the nonlinear characteristics of CMOS using Taylor-series analysis and a BSIM3based model 2. We have analyzed the output-conductance nonlinearity of CMOS and have compared it with t
9、he transconductance nonlinearity. The linearity trend with a down-scaled device is also described in Section II. The capacitance contribution for linearity and substrate network behavior are also analyzed, and their effects are discussed in Section III. Manuscript received May 13, 2002; revised Sept
10、ember 18, 2002. This work was supported in part under the Brain Korea 21 Project, by the Agency for De- fence Development, and by Hynix. TheauthorsarewiththeDepartmentofElectronicandElectricalEngineering, Microwave Application Research Center, Pohang University of Science and Technology Kyoungbuk 79
11、0-784, Korea. (e-mail: kangnarupostech.ac.kr; bmkimpostech.ac.kr) Digital Object Identifier 10.1109/TMTT.2003.808709 II. TRANSCONDUCTANCE AND OUTPUT-CONDUCTANCENONLINEARITIES The BSIM3 model is widely used in circuit simulation tools, but it requires a large data set for accurate modeling and is not
12、 suitable for a simple analysis. However, the model contains all the information for nonlinear behavior. Taylor series are usually used for weakly nonlinear circuit analysis because it is simple. However, it cannot be applicable to highly nonlinear applica- tions such as power amplifiers. In this pa
13、per, Taylor-series anal- ysis is employed and the expansion coefficients are extracted from the BSIM3 model. The drain current in Taylor expansions can be expressed as follows: (1) Assuming that the drain is shorted at a signal frequency, all output-conductance terms (,) and cross mod- ulation terms
14、 (,) are vanished and only transconductance terms (,) remain. In this case, the third-order intercept point (IP3) of gate voltage ampli- tude given as follows in (2) has been used as a device linearity criterion in many previous reports 1: (2) This model is not accurate enough, however, because it d
15、oes not consider output-conductance nonlinearity. To compare output-conductance nonlinearity with transconductance nonlin- earity, the output nonlinear currents from the two components are calculated. For typical CMOS processes, the higher order terms and cross-modulation terms in (1) are very small
16、 and can be ignored to simplify the calculation. In this approxima- tion, the third-order intermodulation currents caused by the transconductance and output-conductance nonlinearities, at a low frequency, are given by (3) (4) whereisthefundamentalvoltageamplitudeatthegateand is the fundamental volta
17、ge at the drain, which can be expressed as (5) 0018-9480/03$17.00 2003 IEEE KANG et al.: LINEARITY ANALYSIS OF CMOS FOR RF APPLICATION973 Fig. 1.TSMC 0.25-?m NMOS transconductance. Fig. 2.TSMC 0.25-?m NMOS output conductance. The TSMC Company Ltd., Taiwan, R.O.C., 0.25m 10m10 NMOS BSIM3v3 model is u
18、sed for this study 4. All Taylor-series parameters are extracted from the dc IV curve of the model. The extracted parameters are shown in Figs. 1 and 2. Fig. 1 shows, andversusfor a constant (V). We selected the gate biasV for comparison because this point is where the transconductance nonlinearity
19、is large with sufficient gain. Fig. 2 shows, , andat the selected gate bias voltage.V is selected as a bias point because this is usual bias voltage for 0.25m NMOS considering load resistance voltage drop and the output-conductance nonlinearity of the MOS is near minimum. Using these parameters and
20、(3)(5), we calculate the output third-order intermodulation current of the circuit given in Fig. 3 for various loads and compare them with the results of har- monic-balance simulation. Two-tone source voltage of 2 mV (50 dBm in 50) is injected to ensure a weakly nonlinear operation. The result is sh
21、own in Fig. 4, where the intermodula- tion currents are shown in ascale. Only with, ,andcoefficients,thecalculationresultmatchesthesim- ulationresultverywell.Whenweincludeandotherhigher order components, the calculations predict the simulated results even better. However, their effects are small and
22、 can be ne- glected in the saturation region of the MOSFET. Howeverin the linear region, the cross-modulation terms are large and should be included to achieve an accurate analysis. The nonlinear currents are dependent on load impedance. When drain voltage swing is small at a low load resistance, th
23、e transconductance is the dominant nonlinear source. At a Fig. 3.NMOS model for linearity analysis. Fig. 4.Output IM3 currents versus load resistance. Fig. 5.Gain and OIP3 versus load resistance. high load resistance, however, the output conductance is the dominant nonlinear source. The decreases of
24、 IM3 at a high load resistance are shunting effect ofand. The output third-order intercept point (OIP3) and power gain for a 300- source resistance are calculated. The results are depicted in Fig. 5. The maximum OIP3 is obtained at a load resistance lower than the value for the maximum gain (). The
25、best linearityisachievedattheloadresistancewheretheoutput-con- ductance nonlinearity increases to a level comparable to the transconductance nonlinearity (). Up to, the funda- mental and intermodulation currents () remain the same and their powers increase at the same rate, proportional to the load
26、resistance and OIP3 increases. The fundamental current stays constant up to, but the intermodulation current from the output-conductance nonlinearity () increases 974IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 51, NO. 3, MARCH 2003 Fig. 6.Linearity of various gate-length MOS (TSMC pro
27、cess). rapidly in this region, and OIP3 decreases. Above, and power gain both decrease. In many RF applications, the load impedance is generally matched to the device output impedance for a maximum power transfer. If we desire a highly linear operation, however, the output impedance should be reduce
28、d from the power-matching impedance. It is desirable to select an output load betweenandfor good RF performances. Tounderstandtheprocess-dependentlinearitytrend,weeval- uate the maximum OIP3 for TSMC 0.35-, 0.25-, and 0.18- m processes. The total gatewidth is 100m with ten fingers. Since the lineari
29、ty varies with output load resistance, we calculate the maximum OIP3s and corresponding load resistances for var- ious current levels and drain bias voltages. As the gate length shortens, the transconductance becomes more linear, but the output conductance becomes more nonlinear. As a result, the ma
30、ximum OIP3 of CMOS does not change for the gate-length variations, as shown in Fig. 6. A shorter gate MOSFET delivers a little better linearity at a high current density, but the improve- ment is negligible and at a lower current density, the same or a slightly worsened linearity is achieved. Howeve
31、r, the maximum OIP3ofashortMOSFEToccursatalowerloadimpedance,and for usual operation level load impedance, the OIP3 is degraded as the gate length is reduced. If the input third-order intercept point (IIP3) is considered, a shorter gate device is much more nonlinear at the same bias current level be
32、cause of its higher gain. Toverifytheaboveconclusionsfrommeasureddata,weeval- uate 0.18- and 0.25- m NMOS devices from Hynix. We mea- sureandcurves using an Agilent 4155 pa- rameter analyzer, and extract, andfrom the measured dc IV data. To obtain smooth data from the measure- ments, we use a data-p
33、rocessing program based on MATLAB. MaximumOIP3sarecalculatedforvariouscurrentdensitiesand bias voltages using (3) and (4), and are depicted in Fig. 7. As shown, the OIP3 of the MOSFET depends only on the current density andbiasvoltage, butdoesnotdepend onthegate length. These trends are identical to
34、 the simulation results. III. HIGH-FREQUENCYEFFECTS DUE TO CAPACITIVECOMPONENTS Previous experimental report shows that the input impedance of CMOS is a major source of nonlinearity at a high frequency Fig. 7.Linearity of various gate-length MOS (Hynix process). Fig. 8.IIP3 from?and?nonlinearity for
35、 various?. 3.Theinputimpedanceconsistsoftwononlinearcomponents, gatesourcecapacitance()andfeedbackcomponentthrough gatedrain capacitance (). The effects ofandon the input nonlinearities are evaluated numerically for various source resistances. To eliminate theMiller effect, the drain is shorted. We
36、simulated IIP3 voltage from the gate nonlin- earity and the results are shown in Fig. 8. The IIP3 voltage from theandnonlinearities are significantly larger than that from transconductance nonlinearity for all source resistances and frequencies, i.e., the intermodulation components gener- ated byand
37、are much smaller than that caused from transconductance. To eliminate theeffect, we add a unity gain voltage-con- trolled voltage source, with input port to the gate and output port to the drain, as shown in Fig. 3. The IIP3 voltage is re- duced by only approximately 1 dB, indicating that the effect
38、 of thenonlinearity is smaller than that of. However, the intermodulation components at the gate are increased for a large load resistance becauseforms a feedback loop for the harmonics, which are generated at the drain, and disturbs device linearity. When we simulate the input nonlinearity with zer
39、o, the gate voltage intermodulation components are re- duced by approximately 8 dB at minimum. For the other ca- pacitance, drainsource capacitance () is small and remains almost constant at the saturation region, and its effect is negli- gible. In summary, the capacitive elements do not generate an
40、y significant harmonics, butinfluences the harmonics by the feedback. Also,andcan reduce the output impedance at a high frequency and effectively reduce the output-conductance non- KANG et al.: LINEARITY ANALYSIS OF CMOS FOR RF APPLICATION975 linearity due to the reduced voltage swing. The output IM
41、3 cur- rent modified by these capacitances can be obtained using the following equations: (6) (7) (8) whereis the voltage gain from the gate to drain. The inter- modulation currents are given by (9) (10) (11) The drain intermodulation voltage is feedback to the gate throughand the feedback effect ca
42、n be calculated as (12) (13) whereis the feedback factor given by (14) The IM3 output current is calculated up to 6 GHz using these simple equations and is compared with the simulation results for various load resistances. They agree very well. The calcu- latedresultshows thatandarethedominantnonlin
43、ear source up to the frequency. At a low frequency,is the dom- inant device nonlinear source for a usual load impedance, but at a high frequency (above4 GHz), the transconductance becomes more important for all load impedance. The effects of conductive substrate and drainsourcesub- strate junction d
44、iode capacitance on CMOS linearity have been studied using the model proposed in 4 and depicted in Fig. 9. In the substrate network, the resistances are considered as linear elements, but the sourcesubstrate and drainsubstrate diodes are always reverse biased, working as nonlinear capacitors. The p-
45、n junction capacitors can be approximated by (15) as follows: (15) Fig. 9.MOSFET substrate network model. Fig. 10.Third-order intermodulation current from output conductance and ?. inwhichisthejunctioncapacitanceatzerobias.Thecapac- itance nonlinear current can then be calculated as follows 5: (16)
46、Using this equation and parameters from 4, we calculate the output third-order intermodulation current generated from the drainsubstrate junction capacitor (). In Fig. 10, we compare it with the intermodulation current generated from output conductance ().is much less than andcanbeneglectedwithalitt
47、leerroruptoamod- erate frequency. However, the difference is reduced proportion- ally at a higher frequency and, above 10 GHz, it may be neces- sary to include the nonlinearity for an accurate analysis. How- ever, this frequency can be varied according to the pad size and substrate doping level. For
48、 a simple calculation, we assume thatis constant and modify (6)(13) to include the following substrate admittance: (17) 976IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 51, NO. 3, MARCH 2003 Fig. 11.Third-order intermodulation current for CMOS with all capacitive elements. Fig. 12.Gain
49、and OIP3 for CMOS including all capacitive elements. The calculated results using our model are compared with har- monic-balance simulation results. As shown in Fig. 11, there are good agreements between the two results. The load-depen- dent nonlinear currents from the transconductance and output conductance, shown in Fig. 11, include all the capacitive ef- fects and substrate network. The OIP3 and gain curves are depicted in Fig. 12. Due to the capacitive shunting effect, the output voltage swing is reduced and the nonlinear current of the output con