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1、_ Maxim Integrated Productsi DUAL DATA? POINTERS? ? WITH AUTO-? SELECT? INCREMENT/? DECREMENT DUAL SERIAL? PORTS HIGH-SPEED? ONE CLOCK-CYCLE? 8051 MICROPROCESSOR 16kB? FLASH MEMORY 1kB? SRAM FOUR? 8-BIT? PARALLEL? PORTS? 1 5 25 0 33 ULTRA-HIGH-SPEED FLASH MICROCONTROLLER ORIGINAL 8051 MIPS ULTRA-HIG
2、H-SPEED FLASH MICROCONTROLLER USERS GUIDE Rev: 10; 3/08 The Ultra-High-Speed Flash Microcontroller Users Guide should be used in conjunction with the data sheet(s) for all ultra-high-speed flash microcontrollers. _ii Ultra-High-Speed Flash Microcontroller Users Guide TABLE OF CONTENTS SECTION 1: Int
3、roduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 SECTION 2: Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 SECTION 3: Architecture . . . . .
4、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 SECTION 4: Programming Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 SECTION 5: CPU Timing . . . . . . . . . . . . . . . . . .
5、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 SECTION 6: Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 SECTION 7: Power Management . . . . . . . . . . . . . . . . . . . . . . . . . .
6、 . . . . . . . . . . . . . . . . . . . . . . . . .7-1 SECTION 8: Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 SECTION 9: Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7、 . . . . . . . . . . . . . . . . .9-1 SECTION 10: I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 SECTION 11: Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8、. . . . .11-1 SECTION 12: Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 SECTION 13: Timed-Access Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 SECTION 14: I
9、nstruction Set Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 SECTION 15: Program Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 REVISION HISTORY . . . . . . . . . . . .
10、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Rev-1 _ Maxim Integrated Products1-1 Ultra-High-Speed Flash Microcontroller Users Guide SECTION 1: INTRODUCTION Maxims ultra-high-speed flash microcontroller is an 8051-compatible microcontroller that prov
11、ides improved performance and power consumption when compared to the original 8051 version. It retains instruction set and object code compatibility with the 8051, yet per- forms the same operations in fewer clock cycles. Consequently, greater throughput is possible for the same crystal speed. As an
12、 alter- native, the device can be run at a reduced frequency to save power. The more efficient design allows a much slower crystal speed to get the same results as an original 8051, using much less power. The fundamental innovation of the ultra-high-speed flash microcontroller is the use of only one
13、 clock per instruction cycle compared with 12 for the original 8051. This results in up to 12 times improvement in performance over the original 8051 architecture and up to four times improvement over other Maxim high-speed microcontrollers. The device provides several peripherals and features in ad
14、di- tion to all of the standard features of an 80C32. These include 16kB/32kB/64kB of on-chip flash memory, 1kB of on-chip RAM, four 8-bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual data pointers, an on-chip watchdog timer, five levels of interrupt priority, and a crystal multip
15、lier. The device provides 256 bytes of RAM for variables and stack; 128 bytes can be reached using direct or indirect addressing, or using indirect addressing only. In addition to improved efficiency, it can operate at a maximum clock rate of 33MHz. Combined with the 12 times performance, this allow
16、s for a maximum performance of 33 million instructions per second (MIPS). This level of computing power is comparable to many 16-bit processors, but without the added expense and complexity if implementing a 16-bit interface. The device incorporates a power-management mode that allows the device to
17、dynamically vary the internal clock speed from 1 clock per cycle (default) to 1024 clocks per cycle. Because power consumption is directly proportional to clock speed, the device can reduce its operating frequency during periods of little switchback. This greatly reduces power consumption. The switc
18、hback feature allows the device to quickly return to highest speed operation upon receipt of an interrupt or serial port activity, allowing the device to respond to external events while in power-management mode. _ Maxim Integrated Products2-1 Ultra-High-Speed Flash Microcontroller Users Guide SECTI
19、ON 2: ORDERING INFORMATION The ultra-high-speed flash microcontroller family follows the part numbering convention shown below. Note that not all combinations of devices may be currently available. Contact a Maxim sales office for up-to-date details. DS89C420-QCL SPEED: L 33MHz? TEMPERATURE: C 0C to
20、 +70C N-40C to+85C MPDIP PACKAGE: Q PLCC? EThin Quad Flat Pack (TQFP)? OPERATING VOLTAGE: 0 +5V? MEMORY TYPE: 9 Flash 3-1_ Ultra-High-Speed Flash Microcontroller Users Guide SECTION 3: ARCHITECTURE This section contains the following information: ALU . . . . . . . . . . . . . . . . . . . . . . . . .
21、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Accumulator . . . . . . . . . . . . . . . . . . . . . . . .
22、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23、 . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Data Pointer(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24、 . . . . . . . . . . . . . .3-2 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25、. . . . .3-2 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Scratchpad Registers (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Stack .
26、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Working Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Program Counter . . . . . .
27、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . .
28、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29、 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30、 . . . . . . . . . . . . . . . . . . .3-4 _3-2 Ultra-High-Speed Flash Microcontroller Users Guide SECTION 3: ARCHITECTURE The architecture is based on the industry-standard 87C52 and executes the standard 8051 instruction set. The core is an accumula- tor-based architecture using internal registers
31、for data storage and peripheral control. This section provides a brief description of each architecture feature. Details concerning the programming model, instruction set, and register description are provided in Section 4. ALU The ALU is responsible for math functions, comparisons, and general deci
32、sion making. The ALU is not used explicitly by software. Instruction decoding prepares the ALU automatically and passes it the appropriate data. The ALU primarily uses two special-function registers (SFRs) as the source and destination for all operations. These are the accumulator and B register. Th
33、e ALU also provides sta- tus information in the program status register. The SFRs are described in the following pages. Special-Function Registers All peripherals and operations that are not explicitly controlled by instructions are controlled through SFRs. All SFRs are described in Section 4. The m
34、ost commonly used registers that are basic to the architecture are also described in the following pages. Accumulator The accumulator is a source and destination for many operations involving math, data movement, and decisions. Although it can be bypassed, most high-speed instructions require the us
35、e of the accumulator (A or ACC) as one argument. B Register The B register is used as the second 8-bit argument in multiply and divide operations. When not used for these purposes, the B reg- ister can be used as a general-purpose register. Program Status Word The program status word holds a selecti
36、on of bit flags that include the carry flag, auxiliary carry flag, general-purpose flag, register bank select, overflow flag, and parity flag. Data Pointer(s) The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This address can point to a data memory loc
37、ation, either on- or off-chip, or a memory-mapped peripheral. When moving data from one memory area to another or from memory to a memory-mapped peripheral, a pointer is needed for both the source and destination. The user can select the active pointer through a dedicated SFR bit (Sel = DPS.0), or c
38、an activate an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR. Stack Pointer The stack pointer denotes the register location at the top of the stack, which is the las
39、t used value. The user can place the stack any- where in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for work- ing registers. I/O Ports Four 8-bit I/O ports are available. Each I/O port is represented by an SFR location, and can
40、 be written or read. The I/O port has a latch that contains the value written by software. In general, software reads the state of external pins during a read operation. Timer/Counters Three 16-bit timer/counters are available. Each timer is contained in two SFR locations that can be written or read
41、 by software. The timers are controlled by other SFRs described in Section 4. UARTs The two UARTs are controlled and accessed by SFRs. Each UART has an address that is used to read and write the UART. The same address is used for both read and write operations, which are distinguished by the instruc
42、tion. Each UART is controlled by its own SFR control register. 3-3_ Ultra-High-Speed Flash Microcontroller Users Guide Scratchpad Registers (RAM) The high-speed core provides 256 bytes of scratchpad RAM for general-purpose data and variable storage. The first 128 bytes are directly available to soft
43、ware. The second 128 are available through indirect addressing. Selected portions of this RAM have other optional functions. Stack The stack is a RAM area that stores return address information during calls and interrupts. The user can also place variables on the stack when necessary. The stack poin
44、ter designates the RAM location that is the top of the stack. Thus, depending on the value of the stack pointer, the stack can be located anywhere in the 256 bytes of RAM. A common location would be in the upper 128 bytes of RAM, as these locations are accessible through indirect addressing only. Wo
45、rking Registers The first 32 bytes of the scratchpad RAM can be used as four banks of eight working registers for high-speed data movement. Using four banks, software can quickly change context by changing to a different bank. In addition to the accumulator, the working registers are commonly used a
46、s data source or destination. Some of the working registers can also be used as pointers to other RAM locations (indirect addressing). Program Counter The program counter (PC) is a 16-bit value that designates the next program address to be fetched. On-chip hardware automatically increments the PC v
47、alue to move to the next program memory location. Address/Data Bus The device addresses a 64kB program and 64kB data memory area that resides in a combination of internal and external memory. When external memory is accessed, ports 0 and 2 are used as a multiplexed address and data bus. Three external memory bus structures are supported. The nonpage mode (traditional 8051) bus structure provides the address MSB on port 2 and multiplexes port 0 between address LSB and data. The page mode 1 bus structure use