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1、EECS 141Fall 1999Discussion Session Week #19/1/99 Tips for using Hspice I. Getting Started Setup the environment: source /usr/eesww/HSPICE/98.2/bin/cshrc.meta Run the simulator on your input file: hspice filename.sp ! filename.lis Use the waveform viewer to see the output awaves Input files must hav
2、e the extension .sp for the waveform viewer to work. Also, the input file must have “.OPTION POST=2” specified. Waveforms can be printed by choosing Tools - Print. View the online documentation acroread /usr/eesww/HSPICE/98.2/docs/hspice.pdf without it the current design complexity would not have be
3、en achievable. Design tools include simulation at the various complexity levels, design verification, layout generation, and design synthesis. An overview of these tools and design methodologies is given in Chapter 8 of this textbook. Furthermore, to avoid the redesign and reverification of frequent
4、ly used cells such as basic gates and arithmetic and memory modules, designers most often resort to cell libraries. These libraries contain not only the layouts, but also provide complete docu- mentation and characterization of the behavior of the cells. The use of cell libraries is, for n+n+ S G D
5、+ DEVICE CIRCUIT GATE MODULE SYSTEM Figure 1.6Design abstraction levels in digital circuits. chapter1.fm Page 16 Friday, January 18, 2002 8:58 AM Section 1.2Issues in Digital Integrated Circuit Design17 instance, apparent in the layout of the Pentium 4 processor (Figure 1.5b). The integer and floati
6、ng-point unit, just to name a few, contain large sections designed using the so- called standard cell approach. In this approach, logic gates are placed in rows of cells of equal height and interconnected using routing channels. The layout of such a block can be generated automatically given that a
7、library of cells is available. The preceding analysis demonstrates that design automation and modular design practices have effectively addressed some of the complexity issues incurred in contempo- rary digital design. This leads to the following pertinent question. If design automation solves all o
8、ur design problems, why should we be concerned with digital circuit design at all? Will the next-generation digital designer ever have to worry about transistors or para- sitics, or is the smallest design entity he will ever consider the gate and the module? The truth is that the reality is more com
9、plex, and various reasons exist as to why an insight into digital circuits and their intricacies will still be an important asset for a long time to come. First of all, someone still has to design and implement the module libraries. Semi- conductor technologies continue to advance from year to year.
10、 Until one has devel- oped a fool-proof approach towards “porting” a cell from one technology to another, each change in technologywhich happens approximately every two yearsrequires a redesign of the library. Creating an adequate model of a cell or module requires an in-depth understanding of its i
11、nternal operation. For instance, to identify the dominant performance parame- ters of a given design, one has to recognize the critical timing path first. The library-based approach works fine when the design constraints (speed, cost or power) are not stringent. This is the case for a large number o
12、f application-specific designs, where the main goal is to provide a more integrated system solution, and performance requirements are easily within the capabilities of the technology. Unfortunately for a large number of other products such as microprocessors, success hinges on high performance, and
13、designers therefore tend to push technology to its limits. At that point, the hierarchical approach tends to become somewhat less attractive. To resort to our previous analogy to software methodologies, a program- mer tends to “customize” software routines when execution speed is crucial; com- piler
14、sor design toolsare not yet to the level of what human sweat or ingenuity can deliver. Even more important is the observation that the abstraction-based approach is only correct to a certain degree. The performance of, for instance, an adder can be sub- stantially influenced by the way it is connect
15、ed to its environment. The interconnec- tion wires themselves contribute to delay as they introduce parasitic capacitances, resistances and even inductances. The impact of the interconnect parasitics is bound to increase in the years to come with the scaling of the technology. Scaling tends to empha
16、size some other deficiencies of the abstraction-based model. Some design entities tend to be global or external (to resort anew to the software analogy). Examples of global factors are the clock signals, used for synchronization in a digital design, and the supply lines. Increasing the size of a dig
17、ital design has a chapter1.fm Page 17 Friday, January 18, 2002 8:58 AM 18INTRODUCTIONChapter 1 profound effect on these global signals. For instance, connecting more cells to a sup- ply line can cause a voltage drop over the wire, which, in its turn, can slow down all the connected cells. Issues suc
18、h as clock distribution, circuit synchronization, and supply-voltage distribution are becoming more and more critical. Coping with them requires a profound understanding of the intricacies of digital circuit design. Another impact of technology evolution is that new design issues and constraints ten
19、d to emerge over time. A typical example of this is the periodical reemergence of power dissipation as a constraining factor, as was already illustrated in the historical overview. Another example is the changing ratio between device and interconnect parasitics. To cope with these unforeseen factors
20、, one must at least be able to model and analyze their impact, requiring once again a profound insight into circuit topol- ogy and behavior. Finally, when things can go wrong, they do. A fabricated circuit does not always exhibit the exact waveforms one might expect from advance simulations. Deviati
21、ons can be caused by variations in the fabrication process parameters, or by the induc- tance of the package, or by a badly modeled clock signal. Troubleshooting a design requires circuit expertise. For all the above reasons, it is my belief that an in-depth knowledge of digital circuit design techn
22、iques and approaches is an essential asset for a digital-system designer. Even though she might not have to deal with the details of the circuit on a daily basis, the under- standing will help her to cope with unexpected circumstances and to determine the domi- nant effects when analyzing a design.
23、Example 1.1Clocks Defy Hierarchy To illustrate some of the issues raised above, let us examine the impact of deficiencies in one of the most important global signals in a design, the clock. The function of the clock signal in a digital design is to order the multitude of events happening in the circ
24、uit. This task can be compared to the function of a traffic light that determines which cars are allowed to move. It also makes sure that all operations are completed before the next one startsa traffic light should be green long enough to allow a car or a pedestrian to cross the road. Under ideal c
25、ir- cumstances, the clock signal is a periodic step waveform with transitions synchronized throughout the designed circuit (Figure 1.7a). In light of our analogy, changes in the traffic lights should be synchronized to maximize throughput while avoiding accidents. The impor- tance of the clock align
26、ment concept is illustrated with the example of two cascaded registers, both operating on the rising edge of the clock (Figure 1.7b). Under normal operating condi- tions, the input In gets sampled into the first register on the rising edge of and appears at the output exactly one clock period later.
27、 This is confirmed by the simulations shown in Figure 1.8c (signal Out). Due to delays associated with routing the clock wires, it may happen that the clocks become misaligned with respect to each other. As a result, the registers are interpreting time indicated by the clock signal differently. Cons
28、ider the case that the clock signal for the second register is delayedor skewedby a value . The rising edge of the delayed clock will postpone the sampling of the input of the second register. If the time it takes to propagate the output of the first register to the input of the second is smaller th
29、an the clock delay, the latter will sample the wrong value. This causes the output to change prematurely, as clearly illus- trated in the simulation, where the signal Out goes high at the first rising edge of instead of chapter1.fm Page 18 Friday, January 18, 2002 8:58 AM Section 1.2Issues in Digita
30、l Integrated Circuit Design19 the second one. In terms of our traffic analogy, cars of a first traffic light hit the cars of the next light that have not left yet. Clock misalignment, or clock skew, as it is normally called, is an important example of how global signals may influence the functioning
31、 of a hierarchically designed system. Clock skew is actually one of the most critical design problems facing the designers of large, high- performance systems. Example 1.2 Power Distribution Networks Defy Hierarchy While the clock signal is one example of a global signal that crosses the chip hierar
32、chy boundaries, the power distribution network represents another. A digital system requires a stable DC voltage to be supplied to the individual gates. To ensure proper operation, this voltage should be stable within a few hundred millivolts. The power distribution system has to provide this stable
33、 voltage in the presence of very large current variations. The resistive nature of the on-chip wires and the inductance of the IC package pins make this a difficult proposition. For example, the average DC current to be supplied to a 100 W-1V microprocessor equals 100 A! The peak current can easily
34、be twice as large, and current demand can readily change from almost zero to this peak value over a short timein the range of 1 nsec or less. This leads to a current variation of 100 GA/sec, which is a truly astounding number. Consider the problem of the resistance of power-distribution wires. A cur
35、rent of 1 A running through a wire with a resistance of 1 causes a voltage drop of 1V. With supply voltages of modern digital circuits ranging between 1.2 and 2.5 V, such a drop is unaccept- In REGISTER (b) Two cascaded registers Out REGISTER skew Figure 1.7Impact of clock misalignment. (c) Simulate
36、d waveforms 0 1 2 3 0 1 2 3 time VoltVolt OutOut In skew (a) Ideal clock waveform t (nsec) (Volt) chapter1.fm Page 19 Friday, January 18, 2002 8:58 AM 20INTRODUCTIONChapter 1 able. Making the wires wider reduces the resistance, and hence the voltage drop. While this sizing of the power network is re
37、latively simple in a flat design approach, it is a lot more complex in a hierarchical design. For example, consider the two blocks below in Figure 1.8a Saleh01. If power distribution for Block A is examined in isolation, the addi- tional loading due to the presence of Block B is not taken into accou
38、nt. If power is routed through Block A to Block B, a larger IR drop will occur in Block B since power is also being consumed by Block A before it reaches Block B. Since the total IR drop is based on the resistance seen from the pin to the block, one could route around the block and feed power to eac
39、h block separately, as shown in Figure 1.8b. Ideally, the main trunks should be large enough to handle all the current flowing through separate branches. Although routing power this way is easier to control and main- tain, it also requires more area to implement. The large metal trunks of power have
40、 to be sized to handle all the current for each block. This requirement forces designers to set aside area for power busing that takes away from the available routing area. As more and more blocks are added, the complex interactions between the blocks determine the actual voltage drops. For instance
41、, it is not always easy to determine which way the current will flow when multiple parallel paths are available between the power source and the consuming gate. Also, currents into the different modules do rarely peak at the same time. All these considerations make the design of the power-distributi
42、on a chal- lenging job. It requires a design methodology approach that supersedes the artificial boundaries imposed by hierarchical design. The purpose of this textbook is to provide a bridge between the abstract vision of digital design and the underlying digital circuit and its peculiarities. Whil
43、e starting from a solid understanding of the operation of electronic devices and an in-depth analysis of the nucleus of digital designthe inverterwe will gradually channel this knowledge into the design of more complex entities, such as complex gates, datapaths, registers, control- lers, and memorie
44、s. The persistent quest for a designer when designing each of the men- tioned modules is to identify the dominant design parameters, to locate the section of the design he should focus his optimizations on, and to determine the specific properties that make the module under investigation (e.g., a me
45、mory) different from any others. Figure 1.8 Power distribution network design. (a) Routing through the block(b) Routing around the block Block ABlock B Block ABlock B Block ABlock B Block ABlock B chapter1.fm Page 20 Friday, January 18, 2002 8:58 AM Section 1.3Quality Metrics of a Digital Design21 T
46、he text also addresses other compelling (global) issues in modern digital circuit design such as power dissipation, interconnect, timing, and synchronization. 1.3Quality Metrics of a Digital Design This section defines a set of basic properties of a digital design. These properties help to quantify
47、the quality of a design from different perspectives: cost, functionality, robustness, performance, and energy consumption. Which one of these metrics is most important depends upon the application. For instance, pure speed is a crucial property in a compute server. On the other hand, energy consumpt
48、ion is a dominant metric for hand-held mobile applications such as cell phones. The introduced properties are relevant at all levels of the design hierarchy, be it system, chip, module, and gate. To ensure consistency in the defini- tions throughout the design hierarchy stack, we propose a bottom-up
49、 approach: we start with defining the basic quality metrics of a simple inverter, and gradually expand these to the more complex functions such as gate, module, and chip. 1.3.1Cost of an Integrated Circuit The total cost of any product can be separated into two components: the recurring expenses or the variable cost, and the non-recurring expenses or the fixed cost. Fixed Cost The fixed cost is independent of the sales volume, the number of products sold. An impor- tant component of the fixed cost of an integrated circuit is the eff