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1、Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Copyright 2008 VITA Page 1 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Copyright 2008 VITA Page 1 of 22 June 30, 2008 VITA 46.3, Serial RapidIOTM on VPX Fabric Connector VITA 46.3, Serial RapidIOT
2、M on VPX Fabric Connector Revision 0.6 Revision 0.6 30-Jun-08 30-Jun-08 OBJECTIVE OBJECTIVE The objectives of this standard are to assign Serial RapidIO 1x/4x links onto the VPX P1/J1 connector and to provide rules and recommendations for the use of the Serial RapidIO links. The objectives of this s
3、tandard are to assign Serial RapidIO 1x/4x links onto the VPX P1/J1 connector and to provide rules and recommendations for the use of the Serial RapidIO links. DRAFT STANDARD DISCLAIMER DRAFT STANDARD DISCLAIMER This draft standard is being prepared by the VITA Standards Organization (VSO) and is NO
4、T approved. Do NOT specify or claim conformance to this draft standard. This draft standard is being prepared by the VITA Standards Organization (VSO) and is NOT approved. Do NOT specify or claim conformance to this draft standard. DISTRIBUTION RESTRICTIONS DISTRIBUTION RESTRICTIONS The distribution
5、 and/or presentation of part or all of this draft is restricted to employees of VITA member companies. Employees of VITA member companies who wish to distribute all or part of this draft to companies or persons who are not members of VITA must obtain written permission from the executive director of
6、 VITA. The distribution and/or presentation of part or all of this draft is restricted to employees of VITA member companies. Employees of VITA member companies who wish to distribute all or part of this draft to companies or persons who are not members of VITA must obtain written permission from th
7、e executive director of VITA. PATENT COVERAGE PATENT COVERAGE VITAs patent policy as posted on VITAs website requires disclosure by VITA members of essential patents that may be required for compliance to this standard. Non VITA members who are granted access to all or part of this proposed draft st
8、andard by the executive director of VITA must agree to the requirements of VITAs patent policy and must disclose any patents which they think may be essential to compliance with this proposed standard. VITAs patent policy as posted on VITAs website requires disclosure by VITA members of essential pa
9、tents that may be required for compliance to this standard. Non VITA members who are granted access to all or part of this proposed draft standard by the executive director of VITA must agree to the requirements of VITAs patent policy and must disclose any patents which they think may be essential t
10、o compliance with this proposed standard. COPYRIGHT NOTICE COPYRIGHT NOTICE Published by VMEbus International Trade Association, PO Box 19658, Fountain Hills, AZ 85269, Copyright 2007 by VMEbus International Trade Association. All rights reserved. Except for employees of VITA member companies, no pa
11、rt of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without prior written permission of the publisher. Published by VMEbus International Trade Association, PO Box 19658, Fountain Hills, AZ 85269, Copyright 2007 by VMEbus International Trade Associati
12、on. All rights reserved. Except for employees of VITA member companies, no part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without prior written permission of the publisher. Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Table
13、of Contents 1 Introduction.8 1.1 Serial RapidIO Technology Overview 8 1.2 Objective 9 1.3 Terminology. 10 1.3.1 Specification Key Words 10 1.3.2 Definitions. 12 1.4 References 13 2 VITA 46.3 Compliance .14 2.1 General Requirements 14 2.2 3U Plug-In Module Minimum Requirements. 14 2.3 6U Plug-In Modu
14、le Minimum Requirements. 14 2.4 Backplane Minimum Requirements . 14 3 Plug-In Module Requirements 15 3.1 Connector Pin Mappings 15 4 Backplane Requirements19 4.1 Connector Pin Mapping. 19 5 Electrical Requirements21 5.1 AC Coupling Capacitors 21 5.2 Impedance 21 6 Example Topologies - Optional 22 Co
15、pyright 2008 VITA Page 2 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Tables Table 1. Plug-in Module P1 Connector Pin Assignments 15 Table 2. Plug-in Module P1 Connector Signal Definitions 16 Table 3 P1 Connector Port/Link Assignments 17 Table 4 Backplane Slot
16、J1 Connector Pin Assignments. 19 Table 5 Backplane J1 Signal Definitions 20 Figures Figure 1 Example Topology. 22 Copyright 2008 VITA Page 3 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Task Group At the time this standard was competed, task group membership in
17、cluded: Name Company Nauman Arshad Curtiss-Wright Controls Embedded Computing Randy Banton Mercury Computer Systems Steve Belvin i-b-s-i Rodger Bird Boeing Ken Boyette Critea Computer Melissa Heckman Bustronic Gorky Chin Curtiss-Wright Controls Embedded Computing David Compston Radstone Stewart Dewa
18、r Curtiss-Wright Controls Embedded Computing Gerard Drewek General Dynamics-AIS Chris Eckert SBS Technologies, Inc. Jim Fedder Tyco Greg Griffith Tyco Bill Hanna Boeing Richard Hodges Parker-Hannafin Richard Jaenicke Mercury Computer Systems Aaron Kaiway Spectrum Signal Processing Emil Kheyfets Curt
19、iss-Wright Controls Embedded Computing Steve Konsowski Northrop Grumman Jing Kwok Curtiss-Wright Controls Embedded Computing Tony Lavely Mercury Computer Systems Michael Monroe Elma Bustronic Corp. Tim Motyka Northrop Grumman Bill Northey FCI Elwood Parsons Foxconn Bob Patterson Tyco David Pepper GE
20、 Fanuc Jim Robles Boeing Copyright 2008 VITA Page 4 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only John Rynearson VITA Jacob Sealander Curtiss-Wright Controls Embedded Computing Mike Shorey Mercury Computer Systems Andrew Spence Amphenol Backplane Systems Jeff Sm
21、ith GHz Systems, Inc. Ivan Straznicky Curtiss-Wright Controls Embedded Computing Bob Sullivan Hybricon Bruce Thomas Curtiss-Wright Controls Embedded Computing Larry Thompson Crane Div., Naval Surface Warfare Center Michael Thompson Pentair Electronic Packaging (Schroff) Dan Toohey Mercury Computer S
22、ystems Bob Tufford Motorola Embedded Communications Computing John Wemekamp Curtiss-Wright Controls Embedded Computing Dean Holman Mercury Computer Systems Comments, Corrections, or Additions Anyone wishing to provide comments, corrections, and/or additions to this proposed draft standard may direct
23、 their input toward the draft editor: Dan Toohey Mercury Computer Systems, Inc 199 Riverneck Road Chelmsford, MA 01824 USA PH: 1-978-967-1888 EMAIL: The best way to provide corrections and small additions is via marking up the specific pages and e-mailing them to the chair. For longer additions, th
24、e chair still prefers to receive textual information via e-mail. If mechanical drawings are involved, they should be done with AutoCAD. This document is being prepared with Microsoft Word 2003 for Windows compatible computers. Copyright 2008 VITA Page 5 of 22 June 30, 2008 Draft Standard VITA46.3, R
25、ev 0.6 Confidential VITA Members Only VSO and Other Standards Information on other standards being developed by the VSO, VME Product Directories, VME Handbooks, and general information on the VME market is available from the VITA office at the address and telephone number listed on the front cover o
26、f this document. Change Bars Once released, change bars will be used in each revision to indicate modifications from the immediately previous revision. Draft Summary This is the preliminary draft of this standard. The original content of this draft standard was presented and agreed upon at the xxx V
27、SO meeting. See the draft history for a summary list of the major changes made to each draft. Draft History Draft No. Date Comments & Major Changes/Updates D0.1 July 15, 2005 Preliminary Draft D0.2 July 22, 2005 Minor changes not distributed D0.3 September 26, 2005 Review comments incorporated drop
28、to a single mandatory port. D0.4 March 13, 2006 Review comments incorporated Added 1x support D0.5 May 15, 2007 Updated backplane connector pin assignments in Table 1 and Table 4 Corrected date mistakes D0.6 June 30, 2008 Removed all references to glyphs Updated the title page to the new VSO format
29、Added/modified rules and permissions to allow user IO mapping onto the Port C and Port D interfaces Updated the Electrical section Copyright 2008 VITA Page 6 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only Issues & Concerns to be Resolved Following are some of the
30、 issues and concerns that need to be resolved before final approval of this proposed standard: 1. Is there any intent, or desire, to cover switch modules in VITA 46.3? 2. Can the protocol dot specs. Reserve any P1 SE pins for future use? Are the P1 SE spares intended to be used by implementers as th
31、ey see fit? 3. Should example topologies be included in this spec.? Copyright 2008 VITA Page 7 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only 1 Introduction The embedded computing industry serving markets needing ruggedized products requires data plane interconne
32、ct technologies which more closely follow the industry state of the art than those currently available. Switched serial technologies are available which provide significant benefits over currently deployed interconnect technologies. The benefits of switched serial interconnect technologies over para
33、llel multi-drop buses include but are not limited to: Higher transaction bandwidth Higher aggregate bandwidth Lower link latency Less contention for the interconnect medium Increased scalability Less routing real estate consumed The VITA 46 (VPX) standard is a proposal for standardization of switche
34、d serial interconnects for VMEbus applications, with specific concern taken to allow deployment in ruggedized environments. There are many candidate technologies for switched serial interconnects. These include without limitation: Ethernet through 10 GBit, Fibre Channel, InfiniBand, Serial RapidIO,
35、PCI Express, Advanced Switching Interconnect and others. Each technology has its pros and cons, and the market will determine which ones will ultimately survive. The data plane proposed defines a “playing field” on which users may implement their preferred serial interconnect. The VPX base standard
36、(VITA 46.0) defines physical features of VPX components. “Dot” standards further define additional sets of protocol layer standards that define specific serial or parallel interconnects used in a system implementation. This standard, VITA 46.3 is one of the “dot” standards within the VPX family of s
37、tandards. It defines the mapping of Serial RapidIO signals to VPX. 1.1 Serial RapidIO Technology Overview RapidIO systems are comprised of end point processing elements and switch processing elements. The RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications whi
38、ch includes the Logical, Common Transport, and Physical layers. The Logical layer specifications define the operations and associated transactions by which end point processing elements communicate with each other. The Common Transport layer defines how transactions are routed from one end point pro
39、cessing element to another through switch processing elements. The Physical Layer defines how adjacent processing elements electrically connect to each other. RapidIO packets are formed Copyright 2008 VITA Page 8 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only thr
40、ough the combination of bit fields defined in the Logical, Common Transport, and Physical Layer specifications. The RapidIO 1x/4x LP-Serial Physical Layer Specification defines a protocol for packet delivery between Serial RapidIO devices including packet and control symbol transmission, flow contro
41、l, error management, and other device to device functions. The 1x/4x LP-Serial Physical Layer Specification has the following properties: Embeds the transmission clock with data using an 8B/10B encoding scheme. Supports one serial differential pair, referred to as one lane, or four ganged serial dif
42、ferential pairs, referred to as four lanes, in each direction. Allows a Common Transport layer between RapidIO 1x/4x LP-Serial Ports and RapidIO Physical Layer 8/16 LP-LVDS ports without packet manipulation. Employs similar retry and error recovery protocols as the RapidIO 8/16 LP-LVDS Physical Laye
43、r Specification. Supports transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane. 1.2 Objective The objectives of this standard are: To assign 1x/4x LP-Serial RapidIO links to the VPX P1 connector. To provide rules and recommendations for the use of the Seri
44、al RapidIO links. The rules, recommendations, and observations included in this standard are intended to be consistent with the RapidIO Specification. It is expected that VITA 46.3 products will comply with RapidIO Physical, Logical, and Transport Specifications in order to maximize interoperability
45、 with other Serial RapidIO hardware and software products. Copyright 2008 VITA Page 9 of 22 June 30, 2008 Draft Standard VITA46.3, Rev 0.6 Confidential VITA Members Only 1.3 Terminology 1.3.1 Specification Key Words To avoid confusion and to make very clear what the requirements for compliance are,
46、many of the paragraphs in this standard are labeled with keywords that indicate the type of information they contain. These keywords are listed below: Rule Recommendation Suggestion Permission Observation Any text not labeled with one of these keywords should be interpreted as descriptive in nature.
47、 These will be written in either a descriptive or a narrative style. The keywords are used as follows: Rule .: Rules form the basic framework of this draft standard. They are sometimes expressed in text form and sometimes in the form of figures, tables or drawings. All rules shall be followed to ens
48、ure compatibility between board and backplane designs. All rules use the “shall“ or “shall not“ words to emphasize the importance of the rule. The “shall“ or “shall not“ words are reserved exclusively for stating rules in this draft standard and are not used for any other purpose. Recommendation .:
49、Wherever a recommendation appears, designers would be wise to take the advice given. Doing otherwise might result in poor performance or awkward problems. Recommendations found in this standard are based on experience and are provided to designers to speed their traversal of the learning curve. All recommendations use the “should“ or “should not“ words to emphasize the importance of the recommendation. The “should“ or “should not“ words are reserved exclusively for stating recommendations