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1、BRITISH STANDARD BS CECC 90115:1994 Specification for Harmonized system of quality assessment for electronic components Blank detail specification Digital gate array integrated circuits Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Unc
2、ontrolled Copy, (c) BSI BS CECC 90115:1994 BSI 02-2000 ISBN 0 580 34520 3 Amendments issued since publication Amd. No.DateComments Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 BSI 02-2000i
3、 Contents Page National forewordii Forewordiii Text of CECC 901151 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 ii BSI 02-2000 National foreword This British Standard has been prepared und
4、er the direction of the Electronic Components Standards Policy Committee (ECL/-). It is identical with CECC 90115:1993 Harmonized system of quality assessment for electronic components. Blank detail specification: Digital gate array integrated circuits published by the European Committee for Electro
5、technical Standardization (CENELEC) Electronic Components Committee (CECC). CECC 90115 was prepared by CECC WG9 Semiconductor integrated circuits and the United Kingdom participation in the drafting was provided by Technical Committee ECL/24, Semiconductors. Scope. The standard is related to non-fin
6、ished products, where the customer is involved in their design, layout and specification. As a consequence, this standard describes requirements for “tools” (e.g. for design, verification test, and measurement), rather than requirements for components. The application of this specification requires
7、that the relevant process technology and the associated manufacturing line are already qualified. Textual errors. When adopting the text of the International Standard, the textual errors listed below were discovered. In the last line of the table in 2.2, “capacitives” should read “capacitive”. In th
8、e second paragraph of 4.3, “caracteristics” should read “characteristics”. The British Standard which implements the CECC Rules of Procedure is BS 9000-2:1991 General requirements for a system for electronic components of assessed quality Part 2: Specification for the national implementation of the
9、CECC system. Detail specification. Detail specification shall comply with the requirements of this Blank Detail Specification and BS CECC 00111-4:1991 Rules of Procedure 11. Specifications. Part 4: Regulations for CECC detail specification. A British Standard does not purport to include all the nece
10、ssary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Cross-references International StandardCorresponding British Standard CECC 90000BS CECC 90000:1991 H
11、armonized system of quality assessment for electronic components. Generic specification: Monolithic integrated circuits Identical CECC 90100BS EN 90100:1993 Harmonized system of quality assessment for electronic components. Sectional specification: Digital monolithic integrated circuits Identical IE
12、C 747-1BS 6493 Semiconductor devices Part 1 Discrete devices Section 1.1:1984 General Identical IEC 748Part 2 Integrated circuits All Parts are identical Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, the CECC title page, pages ii to iv, pages 1 to 6 a
13、nd a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncon
14、trolled Copy, (c) BSI Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 ii BSI 02-2000 Contents Page Forewordiii 1General description3 1.1Definition3 1.2Technology3 2General description of the
15、arrays and test vehicle3 2.1Description of family, arrays, and/or demonstrators3 2.2Library description rules4 2.3Test vehicles (LTV)5 2.3.1General description5 2.3.2LTV types5 2.3.3Electrical characteristics of the LTV5 3Simulation tools5 4Quality assessment procedures6 4.1General Procedures6 4.1.1
16、Qualification of the technology6 4.1.2Lot by lot tests6 4.2Cell library qualification6 4.2.1Design of cells/macros6 4.2.2Qualification of cells or macros6 4.3Design tool qualification6 4.4Customized devices qualification6 Licensed Copy: London South Bank University, London South Bank University, Sat
17、 Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 BSI 02-2000iii Foreword The CENELEC Electronic Components Committee (CECC) is composed of those member countries of the European Committee for Electrotechnical Standardization (CENELEC) who wish to take part in a harmoniz
18、ed System for electronic components of assessed quality. The object of the System is to facilitate international trade by the harmonization of the specifications and quality assessment procedures for electronic components, and by the grant of an internationally recognized Mark, or Certificate, of Co
19、nformity. The components produced under the System are thereby acceptable in all member countries without further testing. This specification has been formally approved by the CECC, and has been prepared for those countries taking part in the System who wish to issue national harmonized specificatio
20、ns for DIGITAL GATE ARRAY INTEGRATED CIRCUITS. It should be read in conjunction with the current regulations for the CECC System. At the date of printing of this specification, the member countries of the CECC are Austria, Belgium, Denmark, Finland, France, Germany, Ireland, Italy, the Netherlands,
21、Norway, Portugal, Spain, Sweden, Switzerland and the United Kingdom, and copies of it can be obtained from the addresses shown on the blue fly sheet. Preface This blank detail specification (BDS) was prepared by CECC WG 9: “INTEGRATED CIRCUITS”. It is based, wherever possible, on the Publications of
22、 the International Electrotechnical Commission and in particular on IEC 747: Semiconductor devices Discrete devices and integrated circuits, and IEC 748: Semiconductor devices Integrated circuits. The text of this specification was circulated to the CECC for voting in the documents listed below and
23、was approved for publication: It is recognized that the layout proposed cannot be applied to all detail specifications based on this document. For instance, it may be preferable to indicate the limiting values in the form of a table when several similar devices appear in the same detail specificatio
24、n. AVIS In accordance with the decision of the CECC Management Committee, this specification is published initially in English and French. The German text will follow as soon as it has been prepared. DocumentDate of VotingReport on the Voting CECC(Secretariat)2648January 1991CECC(Secretariat)2788 Li
25、censed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI iv blank Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:199
26、4 BSI 02-20001 General This document represents a new concept for BDSs, different from the other BDSs published by Working Group 9. This is necessary, because it is related to non-finished products, where the customer is involved in their design, layout and specification. As a consequence, this BDS
27、describes requirements for “tools” (e.g. for design, verification, test, and measurement), rather than requirements for components. The application of this specification requires that the relevant process technology and the associated manufacturing line are already qualified. The following informati
28、on is given for guidance. Scope This BDS relates to Integrated Gate Arrays in accordance with IEC 748: Semiconductor devices Integrated circuits. A gate array is a circuit having a design methodology based on a technological process and function library which elements have been prediffused. The set
29、of such gate arrays shall be defined in terms of complexity: maximum number of equivalent gates maximum percentage of usable gates (where appropriate) die size I/O number. Related documents See 2.1 of CECC 90100 and 2.2 of CECC 90000. Structure of Detail Specifications Clause numbering of DSs shall
30、be in accordance with that of this document. Units, symbols and terminology See 2.3 of CECC 90100 and 2.3 of CECC 90000. Application of Quality Assessment Procedures See 3 of CECC 90100 and CECC 90000. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT
31、+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 2 BSI 02-2000 Layout of front page of detail specification Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 BSI 02-20003 1 General de
32、scription 1.1 Definition TTV: Technology Test Vehicle: (see CQC of ASF) LTV: Library Test Vehicle: the content and use of this vehicle are described in 2.3. LTVs are intended for qualification of library cells and design tools. CD: Demonstrator IC: a circuit implemented with the gate array. The func
33、tions of this circuit are to be defined by the IC manufacturer. It is intended for performance evaluation by users. CC: Customer circuit: a circuit based on the gate array to implement customer circuits. 1.2 Technology The technology employed shall either be defined in a Detail Specification (DS), o
34、r, where there is no suitable DS, by means of a concise description. 2 General description of the arrays and test vehicle 2.1 Description of family, arrays, and/or demonstrators The following shall be specified: power supplies and limiting conditions number of physical gates or cells number of usabl
35、e gates or cells maximum dynamic power dissipation for the device and per MHz or per functional unit number of available buffers per output percentage or number of I/O buffers usable as output number of outputs which can be simultaneously switched under specified conditions (supply voltage, loading,
36、 etc.) for each array of a family: 1) physical layout information including (where appropriate). identification and position of power supply and ground pads identification and position of special pads (oscillators, test pads, etc.) position of the I/O stages locations of active, and interconnection,
37、 zones description of interconnection capability (number of levels, horizontal and vertical grids routing over active areas, etc.) 2) locations of bus or other techniques for supply distribution and prohibited regions 3) die size(s) 4) packaging availability 5) functional description of the test veh
38、icle of customer circuits 6) static characteristics: see library 7) dynamic characteristics: see library and simulation. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 4 BSI 02-2000 2.2 Libr
39、ary description rules The parameters listed below shall be specified. GeneralLibrary For all cells maximum acceptable load tPLH, tPHL worst/best cases of temperature, power supply and technology for a specified fan out and capacitive load or (2) typical values for stated conditions of temperature, p
40、ower supply, fan out and capacitive load variation of tPLH and tPHL in terms of: loading conditions (also capacitive) temperature (3) supply voltage (3) process (3) interconnections name of the function reference of the function logical or analogical symbol of the function truth table and/or sequenc
41、ial diagram number of gates number of elementary cells electrical diagram symbolic topology pin assignment fan in and fan out timing diagrams symbolic description simulation model internal equivalent capacitance CPD For I/O cells only VOH/VOL protection level (ESD, latch-up .) (4) number of used pad
42、s acceptable capacitives loads X X(1) X X X X X X X X X X X X X X X X(1) X(1) X X X(1) X(1) X(1) X(1) X X (1) Optional. (2) At the manufacturers option. (3) Optional except for the typical tPLH, tPHL description. (4) ESD: as in Publication IEC 747-1 chapter 9. Latch-up: as in IEC 47A (Central Office
43、) 252 and 266. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:18 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90115:1994 BSI 02-20005 2.3 Test vehicles (LTV) 2.3.1 General description The LTV described in this document shall be designed and manufact
44、ured in accordance with claimed capability (technology, configuration) and shall allow verification of: interconnection characteristics: 1) line delay (per unit length) where characteristics are given as minimum and maximum based on simulations 2) if applicable, electrical input parameters for simul
45、ation to allow calculation of line delays per unit length (such as simulator input parameters, or library elements such as polysilicon resistors, metallization, etc.) noise immunity: 1) crosstalk, where appropriate 2) static parameters: VIL, VIH, VOL, VOH intrinsic speed of the technology: The maxim
46、um switching speed(s) or frequencies obtainable with one or more of the library elements (such as a ring oscillator, or two stage divider). loading effects on internal cells or macros (circuits) Where loading effects have not been taken into account in the verification of separately accessible funct
47、ions, then a specific test shall be performed: buffers shall: 1) be documented (characteristics simulation results) 2) allow evaluation of their behaviour in respect of influences such as: perturbations: crosstalk on non-active outputs interface: power supply network power consumption. 2.3.2 LTV typ
48、es LTV shall contain a range of cells/macros which is representative of the claimed capability subjected to the satisfaction of the ONS. The cells shall be described in terms of basic functions and shall demonstrate the complexity of functions available for design. At the discretion of the manufactu
49、rer these may be implemented on one or more different test vehicles. With the agreement of the ONS, alternative cells or macros of equivalent complexity may be provided. 2.3.3 Electrical characteristics of the LTV Power supply consumption shall be defined: in static mode in dynamic mode: measured in mA/MHz/gate. The test configurations shall be specified by the manufacturer. 3 Simulation tools A concise description of, or reference to, the