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1、BRITISH STANDARD BS CECC 00013:1985 Harmonized system of quality assessment for electronic components: Basic specification: Scanning electron microscope inspection of semiconductor dice UDC 621.385.833.28:621.382.049.776.2 Licensed Copy: London South Bank University, London South Bank University, Fr
2、i Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 This British Standard, having been prepared under the direction of the Electronic Components Standards Committee, was published under the authority of the Board of BSI and comes into effect on 30 August 1985 BSI 11-1999
3、The following BSI references relate to the work on this standard: Committee reference ECL/- Draft for comment 83/26199 DC ISBN 0 580 14602 2 Committee responsible for this British Standard The preparation of this British Standard was undertaken by the Electronic Components Standards Committee, upon
4、which the following bodies were represented: Association of Control Manufacturers TACMA (BEAMA) Association of Franchised Distributors of Electronic Components British Industrial Measuring and Control Apparatus Manufacturers Association British Standards Society Control and Automation Manufacturers
5、Association (BEAMA) Department of Industry Computers Systems and Electronics Department of Trade Electronic Components Industry Federation Electronic Engineering Association Engineering Equipment Users Association Ministry of Defence National Supervising Inspectorate Post Office Scientific Instrumen
6、t Manufacturers Association Society of British Aerospace Companies Limited Telecommunication Engineering and Manufacturing Association (TEMA) Amendments issued since publication Amd. No.Date of issueComments Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:
7、48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 BSI 11-1999i Contents Page Committee responsibleInside front cover National forewordiii Forewordii 1Scope1 1.1General1 1.2Alternative standards1 2Definitions1 2.1SEM inspection Lot1 2.2Oxide steps1 2.3Multi-level metallisation system1
8、2.4Multi-layered-metal1 2.5Critical areas1 2.6Failed dice1 3Requirements2 3.1Equipment2 3.1.1Scanning electron microscope2 3.1.2Deposition of a conductive film2 3.2Sample selection2 3.2.1Wafer sample selection from a metallisation run2 3.2.2Wafer sample selection from a procured lot2 3.2.3Die sample
9、 selection2 3.2.3.1Non-glassivated devices2 3.2.3.2Glassivated devices2 3.2.3.3Multi-level systems3 3.3Die sample preparation3 3.3.1Deposition of a conductive film3 3.3.2Mounting on specimen holder3 3.4Die sample examination, general requirements3 3.4.1General3 3.4.2Viewing angle3 3.4.3Viewing direc
10、tion3 3.4.4Magnification4 3.5Die sample examination, detail requirements4 3.5.1Discrete semiconductor devices4 3.5.1.1Oxide steps4 3.5.1.2General metallisation4 3.5.2Integrated circuits4 3.5.2.1Oxide steps4 3.5.2.2General metallisation4 3.5.3Multi-layered-metal interconnection systems4 3.6Specimen a
11、fter examination4 3.7Acceptance requirements4 3.7.1General4 3.7.2Single wafer acceptance basis4 3.7.3Lot acceptance basis5 3.8Accept/Reject criteria5 Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 0001
12、3:1985 ii BSI 11-1999 Page 4Documentation5 4.1Photographic5 4.2Information5 4.3Distribution of documentation5 Chart 1 Sample selection from non-glassivated devices10 Chart 2 Sample selection from glassivated devices11 Chart 3 Sample selection from glassivated devices12 Chart 4 Sample selection from
13、glassivated devices13 Chart 5 Sample selection from glassivated devices (procured wafers)14 Chart 6 Sample selection for multi-level systems15 Figure 1 Viewing angle7 Figure 2 Wafer sample selection8 Figure 3 Dice selection on wafer diameter8 Figure 4 Dice selection on wafer segment9 Table 1 Examina
14、tion procedure for sample dice6 Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 BSI 11-1999iii National foreword This British Standard has been prepared under the direction of the Electronic
15、Components Standards Committee. It is identical with CENELEC Electronic Components Committee (CECC) 00013:1984 “Harmonized system of quality assessment for electronic components: Basic specification: Scanning electron microscope inspection of semiconductor dice”. This standard is a harmonized specif
16、ication within the CECC system. Terminology and conventions. The text of the CECC specification has been approved as suitable for publication as a British Standard without deviation. Some terminology and certain conventions are not identical with those used in British Standards; attention is drawn e
17、specially to the following. The comma has been used as a decimal marker. In British Standards it is current practice to use a full point on the baseline as the decimal marker. NOTEThe last part (beginning “and copies”) of paragraph 4 of the foreword is not applicable for this British Standard A Brit
18、ish Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a fron
19、t cover, an inside front cover, pages i to iv, the CECC title page, page ii, pages 1 to 15 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover. Licensed Copy: London So
20、uth Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI iv blank Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI Licensed Copy: London South Bank Univer
21、sity, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 BSI 11-1999 ii Foreword The CENELEC Electronic Components Committee (CECC) is composed of those member countries of the European Committee for Electrotechnical Standardization (CENEL
22、EC) who wish to take part in a harmonized System for electronic components of assessed quality. The object of the System is to facilitate international trade by the harmonization of the specifications and quality assessment procedures for electronic components, and by the grant of an internationally
23、 recognized Mark, or Certificate, of Conformity. The components produced under the System are thereby accepted by all member countries without further testing. This specification has been formally approved by the CECC, and has been prepared for those countries taking part in the System who wish to i
24、ssue national harmonized specifications for SCANNING ELECTRON MICROSCOPE INSPECTION OF SEMICONDUCTOR DICE. It should be read in conjunction with the current regulations for the CECC System. Preface This basic specification was prepared by the ESA/SCCG. It was sponsored administratively by CECC WG 5
25、who made not contribution to the technical contents. The text of this specification was circulated to the CECC for voting in the document indicated below and was approved by the President of the CECC for publication as a CECC Specification. DocumentDate of VotingReport on the Voting CECC(Secretariat
26、) 1384November 1983CECC(Secretariat) 1449A Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 BSI 11-19991 1 Scope 1.1 General This specification describes the equipment and procedures to be use
27、d for the scanning electron microscope (SEM) inspection of discrete semiconductor devices and integrated circuits. When SEM inspection is prescribed in a detail specification, it shall be used in conjunction with the relevant Appendix of the appropriate CECC generic specification, wherein the specif
28、ic accept/reject criteria will be prescribed. 1.2 Alternative standards Where the configuration of a particular component is not in accordance with the examples shown in this specification or where current in-house inspection drawings or standards (accepted in the PID) are to be used, it shall be th
29、e manufacturers responsibility to obtain the formal interpretation from the ONS, or its designated representative, of any deviation. 2 Definitions 2.1 SEM inspection lot a SEM inspection lot is defined as a number of wafers of the same type which are selected from the same diffusion, oxidation and m
30、etallisation run and from which a defined number of wafers shall be examined with the SEM 2.2 oxide steps oxide steps are defined as any sloped or abrupt change in thickness of silicon oxide, silicon nitride and/or any other insulating layers on a semiconductor or integrated circuit 2.3 multi-level
31、metallisation system a multi-level metallisation system consists of two or more layers of metal or any other conductive material which are separated from each other by an insulating material 2.4 multi-layered-metal multi-layered-metal is defined as two or more layers of metal or any other conductive
32、 material used for interconnections that are not isolated from each other by a grown or deposited insulating material 2.5 critical areas critical areas shall be deemed to be those areas where, by virtue of design, an increased possibility of failure is probable. Such areas shall be clearly identifie
33、d by the manufacturer by the provision of an enlarged photograph of the complete die examples of critical areas are: very small distances between conductors very narrow conductors very high and steep oxide steps very small contact windows. 2.6 failed dice failed dice are those which are not acceptab
34、le according to the reject criteria specified Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 00013:1985 2 BSI 11-1999 3 Requirements 3.1 Equipment 3.1.1 Scanning electron microscope The scanning electr
35、on microscope used for this inspection shall meet the following requirements: 3.1.2 Conductive film deposition There shall be a facility for the deposition of a conductive film over the sample dice by vapour deposition or sputtering, if required. 3.2 Sample selection 3.2.1 Wafer sample selection fro
36、m a metallisation run Wafer sample selection shall be made after the metallisation process in accordance with Figure 2. The wafers of more than one SEM inspection lot shall be placed in separate sections of the wafer-holder. If one SEM inspection lot has less wafers than there are places on the wafe
37、r-holder, the wafers shall be placed symmetrically from the outside to the centre of the wafer-holder. One wafer from the edge and one nearest the centre of the wafer-holder shall be taken as samples. In case of small SEM inspection lots, it is permissible to break wafers and to place the pieces in
38、the designated sections of the wafer-holder provided they are big enough for die selection according to 3.2.3. Up to die selection, the selected wafers shall be handled throughout all processing steps in such a manner that they retain their traceability. 3.2.2 Wafer sample selection from a procured
39、lot Selection of wafer samples from a procured lot shall be made as follows: Lot size smaller than 10 wafers One wafer per metallisation run to be selected at random. Lot size of 10 wafers or more Two wafers per metallisation run to be selected at random. 3.2.3 Die sample selection From each wafer s
40、elected in accordance with 3.2.1 or 3.2.2, three dice shall be selected (1) as in Figure 3 or (2) as in Figure 4. 3.2.3.1 Non-glassivated devices Dice from non-glassivated devices shall be selected and examined in accordance with Chart 1. 3.2.3.2 Glassivated devices For the selection of dice from gl
41、assivated devices, there are two possibilities: 1) Selection after etching of the metallisation structure, but before glassivation: If SEM inspection lots consist of 20 or more wafers, the selection and examination shall be in accordance with Chart 2. The wafers from which the dice are selected shal
42、l not be used for further processing. If SEM inspection lots consist of less than 20 wafers, the sample dice may be selected and examined in accordance with either Chart 2 or 3. Wafers from which segments are detached for dice selection may be used for further production. Resolution: 25 nm or better
43、 Magnification: X50 to X20 000 Acceleration voltage: 1 kV to 25 kV The specimen holder shall be so constructed that the specimen may be examined through a tilt angle ranging from 0 to 75 (see Figure 1) It shall be possible to rotate the specimen through 360 over the full range of tilt angle The cham
44、ber for the specimen shall be so constructed that a specimen measuring at least 15 mm 15 mm may be examined The equipment shall be capable of taking photographs. Licensed Copy: London South Bank University, London South Bank University, Fri Dec 08 17:00:48 GMT+00:00 2006, Uncontrolled Copy, (c) BSI
45、BS CECC 00013:1985 BSI 11-19993 If, during the glassivation process, the temperatures used are higher than any temperature used during the metallisation process, minus 50 C, the unglassivated sample dice shall be exposed, in a suitable atmosphere (nitrogen), to the temperature/time characteristic of
46、 the glassivation process. 2) Selection after glassivation: Die samples shall be selected and examined in accordance with Chart 4 and the glassivation shall be etched away without damaging the metallisation of the dice. This can be done when etching away the glassivation from the contact pads of the
47、 devices. For procured wafers (see 3.2.2), sample selection and examination shall be in accordance with Chart 5. 3.2.3.3 Multi-level metallisation systems Each metallisation layer shall be evaluated by detaching a segment (see Figure 4) from the appropriate wafer sample (see Chart 6). The selection
48、of wafer and die samples and die examination shall be in accordance with Chart 6. It is permitted to use the remainder of the wafer sample from which the segment is detached for further processing. If, after breaking any segment, the temperatures used for further processing of the wafers are higher
49、than any temperature used during the metallisation process, minus 50 C, the segments for each metallisation layer shall be exposed, in a suitable atmosphere (nitrogen), to the temperature/time characteristic of the further processing. 3.3 Die sample preparation 3.3.1 Deposition of a conductive film To obtain the required resolution it may be necessary to coat the die samples with a conductive film (for example gold, palladium/gold or carbon). When covering the edges and sides of the die with this film, care shall b