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1、BRITISH STANDARD BS EN 61188-5-6:2003 Printed boards and printed board assemblies Design and use Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides The European Standard EN 61188-5-6:2003 has the status of a British Standard ICS 31.190 ? Licensed Copy: sheffiel
2、dun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS EN 61188-5-6:2003 This British Standard was published under the authority of the Standards Policy and Strategy Committee on 26 June 2003 BSI 26 June 2003 ISBN 0 580 42110 4 National foreword This British Standard
3、is the official English language version of EN 61188-5-6:2003. It is identical with IEC 61188-5-6:2003. The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic assembly technology, which has the responsibility to: A list of organizations represented on this c
4、ommittee can be obtained on request to its secretary. Cross-references The British Standards which implement international or European publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards Correspondence Index”, or by using th
5、e “Search” facility of the BSI Electronic Catalogue or of British Standards Online. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does not of itself confer immunity from l
6、egal obligations. aid enquirers to understand the text; present to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK.
7、 Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 19 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. DateComments Licensed Copy: s
8、heffieldun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI EUROPEAN STANDARD EN 61188-5-6 NORME EUROPENNE EUROPISCHE NORM April 2003 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr
9、Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2003 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61188-5-6:2003 E ICS 31.190 English version Printed boards and printed board assemblies Desi
10、gn and use Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides (IEC 61188-5-6:2003) Cartes imprimes et cartes imprimes quipes Conception et utilisation Partie 5-6: Considrations sur les liaisons pistes-soudures Composants sorties en J sur quatre cts (CEI 61188-5
11、-6:2003) Leiterplatten und Flachbaugruppen - Konstruktion und Anwendung Teil 5-6: Betrachtungen zur Montage (Anschlussflche/Verbindung) - Bauelemente mit J-frmigen Anschlssen auf vier Seiten (IEC 61188-5-6:2003) This European Standard was approved by CENELEC on 2003-03-01. CENELEC members are bound
12、to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Cent
13、ral Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same st
14、atus as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and Uni
15、ted Kingdom. Licensed Copy: sheffieldun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI EN 68118-5-6:0230 - - 2 Foreword The text of document 91/338/FDIS, future edition 1 of IEC 61188-5-6, prepared by IEC TC 91, Electronics assembly technology, was submitted to the I
16、EC-CENELEC parallel vote and was approved by CENELEC as EN 61188-5-6 on 2003-03-01. This European Standard should be read in conjunction with EN 61188-5-1:2002. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national
17、 standard or by endorsement (dop) 2003-12-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2006-03-01 Annexes designated “normative“ are part of the body of the standard. In this standard, annex ZA is normative. Annex ZA has been added by CENELEC. _ E
18、ndorsement notice The text of the International Standard IEC 61188-5-6:2003 was approved by CENELEC as a European Standard without any modification. _ Page 2 EN 6118856:2003 Licensed Copy: sheffieldun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI CONTENTS INTRODUCTI
19、ON.4 1 Scope and object5 2 Normative references .5 3 General information6 3.1 General component description .6 3.2 Marking .6 3.3 Carrier packaging format.6 3.4 Process considerations .6 4 QFJ (square) 6 4.1 Introductory remark .6 4.2 Component description6 4.3 Component dimensions .8 4.4 Solder joi
20、nt fillet design .8 4.5 Land pattern dimensions .10 5 QFJ (rectangular) .12 5.1 Introductory remark .12 5.2 Component description12 5.3 Component dimensions .13 5.4 Solder joint fillet design .14 5.5 Land pattern dimensions .16 Annex ZA (normative) Normative references to international publications
21、with their corresponding European publications .18 Bibliography19 Figure 1 QFJ (square)7 Figure 2 QFJ (square) dimensions .8 Figure 3 Solder joint fillet design of QFJ square component with different levels (see IEC 61188-5-1, Table 5)10 Figure 4 QFJ (square) land pattern dimensions12 Figure 5 QFJ (
22、rectangular).12 Figure 6 QFJ (rectangular) dimensions 14 Figure 7 Solder joint fillet design of QFJ rectangular component with different levels (see IEC 61188-5-1, Table 5)16 Figure 8 QFJ (rectangular) land pattern dimensions.17 Page 3 EN 6118856:2003 Licensed Copy: sheffieldun sheffieldun, na, Fri
23、Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI INTRODUCTION This part of IEC 61188 covers land patterns for components with J leads on four sides. Each clause contains information in accordance with the following format: The proposed land pattern dimensions in this standard are based upo
24、n the fundamental tolerance calculation combined with the given land protrusions and courtyard excesses (see IEC 61188-5-1). The courtyard covers all issues pertaining to normal manufacturing needs. The land pattern dimensions covered in this standard are generally applicable for reflowed solder pas
25、te processes. For immersion soldering processes (e.g. wave, jet, drag soldering), lands may have to be modified to prevent shadowing and shorting (e.g. by extending land length parallel to the direction of motion of the board and/or provision of solder thieves). This specification offers a threefold
26、 land pattern dimensioning (levels 1, 2, and 3) on the basis of a threefold set of land protrusions and courtyard excesses maximum (max.), median (mdn.), and minimum (min.). Each land pattern has been assigned an identification number to indicate the characteristics of the specific robustness of the
27、 land patterns. Users also have the opportunity to organize the information to suit their particular design. This standard assumes that land dimensions are always larger than component termination or lead outlines. If a user has good reason to use solder resist to limit wetting on a land, or to use
28、lands smaller than component terminations, or to apply a concept different from that of IEC 61188-5-1, this standard may not apply. It is the responsibility of the user to verify the surface mounting devices (SMD) land patterns used for achieving an undisturbed mounting process, including testing, a
29、nd an ensured reliability for the product stress conditions when in use. Dimensions of the components listed in this standard are those available on the market, and are for reference purposes only. Page 4 EN 6118856:2003 Licensed Copy: sheffieldun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006,
30、 Uncontrolled Copy, (c) BSI PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES DESIGN AND USE Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides 1 Scope and object This part of IEC 61188 provides information on land pattern geometries used for the surface attachment o
31、f electronic components with J leads on four sides. The object of this standard is to provide the appropriate size, shape and tolerances of surface mount land patterns so as to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and reworking of resulting
32、 solder joints. Each clause contains a specific set of criteria, setting out details on the component, the component dimensions, the solder joint design and the land pattern dimensions. NOTE The acronym QFJ is the naming convention used by Japan; the acronym PLCC is the naming convention used by the
33、 USA for these components. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.
34、 IEC 60068-2-58, Environmental testing Part 2-58: Tests Test Td: Test methods for solderability, resistance to dissolution of metallization and soldering heat of surface mounting devices (SMD) IEC 60191-2, Mechanical standardisation of semiconductor devices Part 2: Dimensions IEC 61188-5-1, Printed
35、boards and printed board assemblies Design and use Part 5-1: Attachment (land/joint) considerations Generic requirements IEC 61760-1, Surface mounting technology Part 1: Standard method for the specification of surface mounting components (SMDs) Page 5 EN 6118856:2003 Licensed Copy: sheffieldun shef
36、fieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI 3 General information 3.1 General component description The component consists of quad flat J-lead packages with terminations, which extend beyond the package outlines. The shape of the packages can be either square or recta
37、ngular. These terminations typically separate the body of the package from the packaging and interconnect structure (P&IS) for reasons of clearing, inspecting or accommodating differences in thermal expansion. In plastic leaded chip carriers, the primary packaging distinction concerns the point at w
38、hich a chip is incorporated into the package. A pre-molded package is supplied as a leaded body with an open cavity for chip attachment. A post-molded body part typically has the chip attached to a lead frame with an insulating plastic body molded around the assembly. 3.2 Marking The QFJ (square and
39、 rectangular) families of parts are generally marked with the manufacturers part numbers, name or symbol, and a pin 1 indicator. Some parts may have a pin 1 feature in the case shape instead of a pin 1 marking. Additional markings may include date-code manufacturing lot and/or manufacturing location
40、. 3.3 Carrier packaging format The carrier packaging format may be provided in tubes but embossed carrier taping is preferred for best handling and high volume applications. Bulk packaging is not acceptable because of lead coplanarity required for placement and soldering. 3.4 Process considerations
41、QFJ packages are normally processed by reflow solder operations (see IEC 60068-2-58). High lead-count fine pitch parts may require special processing outside the normal pick/place and reflow manufacturing operations. 4 QFJ (square) 4.1 Introductory remark This clause provides the component and land
42、pattern dimensions for square QFJ (quad flat J- lead) components. Basic construction is also covered. Figures 2 and 3 provide a listing of the tolerances and target solder joint dimensions used to arrive at the land pattern dimensions. 4.2 Component description QFJs are widely used in variety of app
43、lications for commercial, industrial or military electronics. 4.2.1 Basic construction See Figure 1. Page 6 EN 6118856:2003 Licensed Copy: sheffieldun sheffieldun, na, Fri Nov 10 17:57:58 GMT+00:00 2006, Uncontrolled Copy, (c) BSI IEC 3270/02 Figure 1 QFJ (square) QFJs (quad flat J-lead packages) ar
44、e employed where a hermetic seal is not required. Other constraints include a limited temperature range (typically 0 C or 70 C) and nominal environmental protection. QFJs have the advantage of low cost as compared to ceramic packages. 4.2.2 Termination materials High lead-end coplanarity in surface
45、mounted lead chip carriers is an important factor in reliable solder attachment to the printed board. Planarity may be measured from the lowest three leads of a leaded package. Coplanarity of 0,1 mm maximum is recommended with a preference for 0,05 mm. The pre-molded plastic chip carrier was designe
46、d to be connected to the packaging and interconnection (P&l) substrate by means of a socket. Spring pressure on both sides of the package is intended to constrain movement as well as allow for substrate warpage as high as 0,5 %. Solder attach to the P&l substrate is also possible. The design is also
47、 intended to make use of silicone encapsulate technology for chip coverage and protection. The pre- and post-molded plastic leaded chip carrier is composed of a composite metal/dielectric assembly that includes a conductor lead frame and a molded insulating body. In both types of plastic chip carrie
48、rs, all necessary plating operations are performed by the package manufacturer to eliminate tinning or plating by the user. 4.2.3 Marking All parts shall be marked with a part number and “Pin 1” location. The “Pin 1” location may be molded into the plastic body or marked with ink. 4.2.4 Carrier pack
49、age format The carrier package format for flat packs may be provided in tubes but, in most instances, flat packs are delivered in embossed taping. 4.2.5 Process considerations Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 C. Each cycle shall consist of a 60 s exposure at 235 C. Parts must also be capable of withstanding a minimum of 10 s