《IEEE-61523-3-2004.pdf》由会员分享，可在线阅读，更多相关《IEEE-61523-3-2004.pdf（96页珍藏版）》请在三一文库上搜索。
1、 INTERNATIONAL STANDARD IEC 61523-3 First edition 2004-09 IEEE 1497 Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process Reference number IEC 61523-3(E):2004 IEEE Std. 1497(E):2001 Copyright The Institute of Electrical and Electronics Engineers,
2、 Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in
3、 the 60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1. Consolidated editions The IEC is now publishing consolidated versions of its publications. For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendm
4、ent 1 and the base publication incorporating amendments 1 and 2. Further information on IEC publications The technical content of IEC publications is kept under constant review by the IEC, thus ensuring that the content reflects current technology. Information relating to this publication, including
5、 its validity, is available in the IEC Catalogue of publications (see below) in addition to new editions, amendments and corrigenda. Information on the subjects under consideration and work in progress undertaken by the technical committee which has prepared this publication, as well as the list of
6、publications issued, is also available from the following: IEC Web Site (www.iec.ch) Catalogue of IEC publications The on-line catalogue on the IEC web site (www.iec.ch/searchpub) enables you to search by a variety of criteria including text searches, technical committees and date of publication. On
7、-line information is also available on recently issued publications, withdrawn and replaced publications, as well as corrigenda. IEC Just Published This summary of recently issued publications (www.iec.ch/online_news/ justpub) is also available by email. Please contact the Customer Service Centre (s
8、ee below) for further information. Customer Service Centre If you have any questions regarding this publication or need further assistance, please contact the Customer Service Centre: Email: custserviec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 Copyright The Institute of Electrical and Electron
9、ics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the el
10、ectronic design process INTERNATIONAL STANDARD IEC 61523-3 First edition 2004-09 IEEE 1497 Commission Electrotechnique Internationale International Electrotechnical Commission IEEE 2004 Copyright - all rights reserved IEEE is a registered trademark in the U.S. Patent any IEC National Committee inter
11、ested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance wi
12、th conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested
13、IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible fo
14、r the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between
15、 any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) Attention
16、is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 61523-3 has been processed through IEC technical committee 93: Design au
17、tomation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1497 (2001) 93/191/FDIS 93/196/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been dra
18、fted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2006. IEC 61523 consists of the following parts, under the general title Delay and power calculation standards: IEC 61523-1, Part 1: Integrated circuit delay an
19、d power calculation systems Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 3 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 No
20、t for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- IEC 61523-2, Part 2: Pre-layout delay calculation specification of CMOS ASIC libraries IEC/IEEE 61523-3, Part 3: Standard Delay Format (SDF) for the electronic process Published by IEC under l
21、icence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 4 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction
22、 or networking permitted without license from IHS -,-,- IEC/IEEE Dual Logo International Standards This Dual Logo International Standard is the result of an agreement between the IEC and the Institute of Electrical and Electronics Engineers, Inc. (IEEE). The original IEEE Standard was submitted to t
23、he IEC for consideration under the agreement, and the resulting IEC/IEEE Dual Logo International Standard has been published in accordance with the ISO/IEC Directives. IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Ass
24、ociation (IEEE-SA) Standards Board. The IEEE develops its standards through a consensus development process, approved by the American National Standards Institute, which brings together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are not necessari
25、ly members of the Institute and serve without compensation. While the IEEE administers the process and establishes rules to promote fairness in the consensus development process, the IEEE does not independently evaluate, test, or verify the accuracy of any of the information contained in its standar
26、ds. Use of an IEC/IEEE Dual Logo International Standard is wholly voluntary. The IEC and IEEE disclaim liability for any personal injury, property or other damage, of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or indirectly resulting from the publicati
27、on, use of, or reliance upon this, or any other IEC or IEEE Standard document. The IEC and IEEE do not warrant or represent the accuracy or content of the material contained herein, and expressly disclaim any express or implied warranty, including any implied warranty of merchantability or fitness f
28、or a specific purpose, or that the use of the material contained herein is free from patent infringement. IEC/IEEE Dual Logo International Standards documents are supplied “AS IS”. The existence of an IEC/IEEE Dual Logo International Standard does not imply that there are no other ways to produce, t
29、est, measure, purchase, market, or provide other goods and services related to the scope of the IEC/IEEE Dual Logo International Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change brought about through developments in the state of the ar
30、t and comments received from users of the standard. Every IEEE Standard is subjected to review at least every five years for revision or reaffirmation. When a document is more than five years old and has not been reaffirmed, it is reasonable to conclude that its contents, although still of some valu
31、e, do not wholly reflect the present state of the art. Users are cautioned to check to determine that they have the latest edition of any IEEE Standard. In publishing and making this document available, the IEC and IEEE are not suggesting or rendering professional or other services for, or on behalf
32、 of, any person or entity. Neither the IEC nor IEEE is undertaking to perform any duty owed by any other person or entity to another. Any person utilizing this, and any other IEC/IEEE Dual Logo International Standards or IEEE Standards document, should rely upon the advice of a competent professiona
33、l in determining the exercise of reasonable care in any given circumstances. Interpretations Occasionally questions may arise regarding the meaning of portions of standards as they relate to specific applications. When the need for interpretations is brought to the attention of IEEE, the Institute w
34、ill initiate action to prepare appropriate responses. Since IEEE Standards represent a consensus of concerned interests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason, IEEE and the members of its societies and Standards
35、 Coordinating Committees are not able to provide an instant response to interpretation requests except in those cases where the matter has previously received formal consideration. Comments for revision of IEC/IEEE Dual Logo International Standards are welcome from any interested party, regardless o
36、f membership affiliation with the IEC or IEEE. Suggestions for changes in documents should be in the form of a proposed change of text, together with appropriate supporting comments. Comments on standards and requests for interpretations should be addressed to: Secretary, IEEE-SA Standards Board, 44
37、5 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331, USA and/or General Secretary, IEC, 3, rue de Varemb, PO Box 131, 1211 Geneva 20, Switzerland. Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics E
38、ngineers, Inc., provided that the appropriate fee is paid to Copyright Clearance Center. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service, 222 Rosewood Drive, Danvers, MA 01923 USA; +1 978 750 8400. Permission to photocopy portions of any individua
39、l standard for educational classroom use can also be obtained through the Copyright Clearance Center. NOTE Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken wit
40、h respect to the existence or validity of any patent rights in connection therewith. The IEEE shall not be responsible for identifying patents for which a license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its
41、 attention. Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 5 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04
42、/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 5 December 2001 IEEE-SA Standards Board Abst
43、ract: The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing an
44、alysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the formats contents will find it useful. Keywords: computer, computer languages,
45、delay, delay backannotation, digital systems, electron- ic systems, hardware, hardware design, SDF, timing, timing analysis, timing backannotation, timing verification Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 6 Copyright The Inst
46、itute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Copyright 2001 IEEE. All rights reserved. iii The St
47、andard Delay Format (SDF) was designed to serve as a simple textual medium for communicating timing information and constraints between EDA tools. The original version was designed by Rajit C. Chan- dra in 1990 while at Cadence Design Systems, and was intended as a means of communicating macrocell a
48、nd interconnect delays from Gate Ensemble to Verilog-XL, Veritime and other stand-alone tools requiring timing data. Because it was originally targeted for annotation to tools using the Verilog language, many SDF constructs are analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify block will fi nd many of the SDF constructs familiar, such as SETUP and PATHPULSE. SDF also includes constructs for annotating interconnect delays, and can be used for forward annotation by specifying path del