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1、 INTERNATIONAL STANDARD IEC 61691-5 First edition 2004-10 IEEE 1076.4 Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit) modeling specification Reference number IEC 61691-5(E):2004 IEEE Std. 1076.4(E):2000 Copyright The Institute of Electrical and Electronics Engineer
2、s, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/20/2007 09:39:05 MDTNo reproduction or networking permitted without license from IHS -,-,- Publication numbering As from 1 January 1997 all IEC publications are issued with a designation
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9、onics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/20/2007 09:39:05 MDTNo reproduction or networking permitted without license from IHS -,-,- Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit)
10、 modeling specification INTERNATIONAL STANDARD IEC 61691-5 First edition 2004-10 IEEE 1076.4 Commission Electrotechnique Internationale International Electrotechnical Commission Copyright IEEE 2004 All rights reserved IEEE is a registered trademark in the U.S. Patent any IEC National Committee inter
11、ested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance wi
12、th conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested
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16、is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 61691-5 has been processed through IEC technical committee 93: Design au
17、tomation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1076.4 (2000) 93/194/FDIS 93/199/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been d
18、rafted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2005. 4IEC 61691-5:2004(E) IEEE 1076.4-2000(E) Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. Copyright The Institute of Electrical
19、 and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/20/2007 09:39:05 MDTNo reproduction or networking permitted without license from IHS -,-,- IEC 61691 consists of the following parts, under the general title Beha
20、vioural languages: IEC/IEEE 61691-1-1, Part 1: VHDL language reference manual IEC 61691-2, Part 2: VHDL multilogic system for model interoperability IEC 61691-3-1, Part 3-1: Analog description in VHDL (under consideration) IEC 61691-3-2, Part 3-2: Mathematical operation in VHDL IEC 61691-3-3, Part 3
21、-3: Synthesis in VHDL IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration) IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under consideration) IEC/IEEE 61691-4, Part 4: Verilog hardware description language IEC/IEEE 61691-5, Part 5: VITAL ASIC (application specific integrat
22、ed circuit) modeling specification 5IEC 61691-5:2004(E) IEEE 1076.4-2000(E) Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/99725
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42、l validity or scope of those patents that are brought to its attention. 6IEC 61691-5:2004(E) IEEE 1076.4-2000(E) Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELice
43、nsee=NASA Technical Standards 1/9972545001 Not for Resale, 04/20/2007 09:39:05 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standard for VITAL ASIC (Application Specifi c Integrated Circuit) Modeling Specifi cation Sponsor Design Automation Standards Committee of th
44、e IEEE Computer Society Approved 21 September 2000 IEEE-SA Standards Board Abstract: The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specifi cation is defi ned in this standard. This modeling specifi cation defi nes a methodology which promotes the development of highly accurate, ef
45、fi cient simulation models for ASIC (Application-Specifi c Integrat- ed Circuit) components in VHDL. Keywords: ASIC, computer, computer languages, constraints, delay calculation, HDL, modeling, SDF, timing, Verilog, VHDL 7IEC 61691-5:2004(E) IEEE 1076.4-2000(E) Published by IEC under licence from IE
46、EE. 2004 IEEE. All rights reserved. Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/20/2007 09:39:05 MDTNo reproduction or networking permitted without license from IHS -,-,
47、- Copyright 2001 IEEE. All rights reserved. The objectives of the VITAL (VHDL Initiative Towards ASIC Libraries) initiative can be summed up in one sentence: Accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of mod
48、el development. The VITAL ASIC modeling specification is a revision of the IEEE 1076.4-1995, IEEE Standard for VITAL ASIC Modeling Specification. Several new modeling enhancements have been added to the standard and several usability issues which have been raised with the 1995 standard have been addressed. The new enhancements and usability improvements addressed include: Standardized ASIC memory models Support of IEEE VHDL93 and SDF 1497 standards Multisource interconnect timing simulation SKEW constraint timing checks Timing constraint