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1、SURFACE VEHICLE RECOMMENDED PRACTICE Submitted for recognition as an American National Standard Physical Layer, 250K bits/s, Twisted Shielded Pair SAE Technical Standards Board Rules provide that: “This report is published by SAE to advance the state of technical and engineering sciences. The use of
2、 this report is entirely voluntary, and its applicability and suitability for any particular use, including any patent infringement arising therefrom, is the sole responsibility of the user.” SAE reviews each technical report at least every five years at which time it may be reaffirmed, revised, or
3、cancelled. SAE invites your written comments and suggestions. TO PLACE A DOCUMENT ORDER: (724) 776-4970 FAX: (724) 776-0790 SAE WEB ADDRESS: http:/www.sae.org Copyright 1999 Society of Automotive Engineers, Inc. All rights reserved.Printed in U.S.A. Issued1994-12 Revised1999-10 Superseding J1939/11
4、DEC1994 REV. J1939-11OCT1999 ForewordThis series of SAE Recommended Practices have been developed by the Truck and Bus Control and Communications Network Subcommittee of the Truck and Bus Electrical Committee. The objectives of the subcommittee are to develop information reports, recommended practic
5、es, and standards concerned with the requirements design and usage of devices which transmit electronic signals and control information among vehicle components. The usage of these recommended practices is not limited to truck and bus applications. Other applications may be accommodated with immedia
6、te support being provided for construction and agricultural equipment, and stationary power systems. These SAE Recommended Practices are intended as a guide toward standard practice and are subject to change to keep pace with experience and technical advances. TABLE OF CONTENTS 1.Scope. 2 2.Referenc
7、es 3 2.1Applicable Publications 3 2.1.1SAE Publications. 3 2.1.2ISO Publication . 3 2.1.3Military Publication. 3 2.2Related Publication 3 2.2.1ISO Publications 3 3.Network Physical Description 3 3.1Physical Layer. 3 3.2Physical Media 3 3.3Differential Voltage. 4 3.4Bus Levels 4 3.5Bus Levels During
8、Arbitration 4 3.6Common Mode Bus Voltage Range. 4 3.7Bus Termination 4 3.8Internal Resistance 4 3.9Differential Internal Resistance 4 3.10Internal Capacitance 4 3.11Differential Internal Capacitance 4 3.12Bit Time 4 3.13Internal Delay Time 6 Copyright SAE International Provided by IHS under license
9、with SAE Not for ResaleNo reproduction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 2 - 3.14CAN Bit Timing Requirements. 8 4.Functional Description 9 5.Electrical Specification. 9 5.1Electrical Data. 9 5.1.1Electronic Control Unit 9 5.1.1.1Absolute Maximum Rati
10、ngs .10 5.1.1.2DC Parameters.10 5.1.1.3AC Parameters.11 5.1.2Bus VoltagesOperational11 5.1.3Electrostatic Discharge (ESD)11 5.1.4Example Physical Layer Circuits11 5.2Physical Media Parameters .11 5.2.1Bus Line 12 5.2.2Topology12 5.2.3Terminating Resistor.13 5.2.4Shield Termination13 5.3Connector Spe
11、cifications.14 5.3.1Connector Electrical Performance Requirements .14 5.3.2Connector Mechanical Requirements15 6.Conformance Tests.16 6.1Recessive Output of the ECUs 16 6.2Internal Resistance of CAN_H and CAN_L17 6.3Internal Differential Resistance.17 6.4Recessive Input Threshold of an ECU 18 6.5Dom
12、inant Output of an ECU.18 6.6Dominant Input Threshold of an ECU19 6.7Internal Delay Time.19 7.Discussion of Bus Faults.20 7.1Loss of Connection to Network.20 7.2Node Power or Ground Loss 20 7.3Unconnected Shield20 7.4Open and Short Failures20 8.Notes.22 8.1Marginal Indicia 22 Appendix A Example Phys
13、ical Layer Circuits23 A.1Example 1 Physical Layer.23 A.2Example 2 Physical Layer.23 A.3Example 3 Physical Layer.25 Appendix B Recommended Cable Termination Procedure.26 Appendix C Recommended Cable Splice Procedure.27 Appendix D Recommended Cable Repair Procedure 29 1. ScopeThese SAE Recommended Pra
14、ctices are intended for light- and heavy-duty vehicles on- or off-road as well as appropriate stationary applications which use vehicle derived components (e.g., generator sets). Vehicles of interest include but are not limited to: on- and off-highway trucks and their trailers; construction equipmen
15、t; and agricultural equipment and implements. Copyright SAE International Provided by IHS under license with SAE Not for ResaleNo reproduction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 3 - The purpose of these documents is to provide an open interconnect sys
16、tem for electronic systems. It is the intention of these documents to allow electronic devices to communicate with each other by providing a standard architecture. 2.ReferencesGeneral information regarding this series of recommended practices is found in SAE J1939. 2.1Applicable PublicationsThe foll
17、owing publications form a part of this specification to the extent specified herein. Unless otherwise indicated, the latest issue of SAE publications shall apply. 2.1.1 SAE PUBLICATIONSAvailable from SAE, 400 Commonwealth Drive, Warrendale, PA 15096-0001. SAE J1113/13Electromagnetic Compatibility Me
18、asurement Procedure for Vehicle Components Part 13Immunity to Electrostatic Discharge (R)SAE J1128Low-Tension Primary Cable (R)SAE J1939 (Draft)Recommended Practice for a Serial Control and Communication Vehicle Network 2.1.2 ISO PublicationAvailable from ANSI, 11 West 42nd Street, New York, NY 1003
19、6-8002. (R)ISO 6722 Road vehiclesUnscreened low-tension cables 2.1.3 Military PublicationAvailable from DODSSP, Subscripton Services Desk, Building 4D, 700 Robins Avenue, Philadelphia, PA 19111-5094. (R)MIL-C-85485Cable, Electric, Filter Line 2.2Related PublicationThe following publication is provid
20、ed for information purposes only and is not a required part of this document. 2.2.1 ISO PUBLICATIONAvailable from ANSI, 11 West 42nd Street, New York, NY 10036-8002. ISO 11898Road vehiclesInterchange of digital informationController Area Network (CAN) for high speed communication. 3. Network Physica
21、l Description 3.1Physical LayerThe physical layer is a realization of an electrical connection of a number of ECUs (Electronic Control Units) to a network. The total number of ECUs will be limited by electrical loads on the bus line. This maximum number of ECUs is fixed to 30, on a given segment, du
22、e to the definition of the electrical parameters given in the present specification 3.2Physical MediaThis document defines a physical median of shielded twisted pair. These 2 wires have a characteristic impedance of 120 and are symmetrically driven with respect to the electrical currents. The design
23、ations of the individual wires are CAN_H and CAN_L. The names of the corresponding pins of the ECUs are also denoted by CAN_H and CAN_L, respectively. The third connection for the termination of the shield is denoted by CAN_SHLD. 3.3Differential VoltageThe voltages of CAN_H and CAN_L relative to gro
24、und of each individual ECU are denoted by VCAN_H and VCAN_L. The differential voltage between VCAN_H and VCAN_L is defined by Equation 1: Vdiff = VCAN_H VCAN_L (Eq.1) Copyright SAE International Provided by IHS under license with SAE Not for ResaleNo reproduction or networking permitted without lice
25、nse from IHS -,- SAE J1939-11 Revised OCT1999 - 4 - 3.4Bus LevelsThe bus lines can have one of the two logical states, recessive or dominant (see Figure 1). In the recessive state, VCAN_H and VCAN_L are fixed to a mean voltage level. Vdiff is approximately zero on a terminated bus. The recessive sta
26、te is transmitted during bus idle or a recessive bit. The dominant state is represented by a differential voltage greater than a minimum threshold. The dominant state overwrites the recessive state and is transmitted during a dominant bit. 3.5Bus Levels During ArbitrationA dominant and recessive bit
27、 imposed on the bus lines during a given bit time by two different ECUs will result in a dominant bit. FIGURE 1PHYSICAL BIT REPRESENTATION 3.6Common Mode Bus Voltage RangeThe common mode bus voltage is defined as the boundary voltage levels of CAN_H and CAN_L, measured with respect to the individual
28、 ground of each ECU, for which proper operation is guaranteed when all ECUs are connected to the bus line. (R)3.7Bus TerminationThe bus line is electrically terminated at each end with a load resistor denoted by RL. RL shall not be located within an ECU because the bus will lose termination if one o
29、f these ECUs is disconnected (see Figure 2). (Also see 5.2.3 for resistor characteristics.) 3.8Internal ResistanceThe internal resistance, Rin, of an ECU is defined as the resistance seen between CAN_H (or CAN_L) and ground during the recessive state, with the ECU disconnected from the bus line (see
30、 Figure 3). 3.9Differential Internal ResistanceThe differential internal resistance, Rdiff, is defined as the resistance seen between CAN_H and CAN_L during the recessive state, with the ECU disconnected from the bus line (see Figure 4). 3.10Internal CapacitanceThe internal capacitance, Cin, of an E
31、CU is defined as the capacitance seen between CAN_H (or CAN_L) and ground during the recessive state, with the ECU disconnected from the bus line (see Figure 3). 3.11Differential Internal CapacitanceThe differential internal capacitance, Cdiff, of an ECU is defined as the capacitance seen between CA
32、N_H and CAN_L during the recessive state, with the ECU disconnected from the bus line (see Figure 4). 3.12Bit TimeThe bit time, tB, is defined as the duration of one bit (see Figure 5). Bus management functions executed within this bit time, such as ECU synchronization behavior, network transmission
33、 delay compensation, and sample point positioning, are defined by the programmable bit timing logic of the CAN protocol IC (Integrated Circuit). The bit time for this document is 4 s corresponding to 250 Kbit/s. Various names for the bit segments are used by suppliers of CAN protocol ICs and it is p
34、ossible that two bit segments are defined as one. Copyright SAE International Provided by IHS under license with SAE Not for ResaleNo reproduction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 5 - FIGURE 2PHYSICAL LAYER FUNCTIONAL Copyright SAE International Pro
35、vided by IHS under license with SAE Not for ResaleNo reproduction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 6 - FIGURE 3ILLUSTRATION OF INTERNAL CAPACITANCE AND RESISTANCE OF AN ECU IN THE RECESSIVE STATE FIGURE 4ILLUSTRATION OF DIFFERENTIAL INTERNAL CAPACIT
36、ANCE AND RESISTANCE OF AN ECU IN THE RECESSIVE STATE FIGURE 5PARTITION OF THE BIT a. SYNC SEGThis part of the bit time is used to synchronize the various ECUs on the bus. An edge is expected within this bit segment. b. PROP SEGThis part of the bit time is used to compensate for the physical delay ti
37、mes within the network. These delay times are caused by the propagation time of the bus line and the internal delay time of the ECUs. c. PHASE SEG1, PHASE SEG2These Phase-Buffer-Segments are used to compensate for phase-errors and can be lengthened or shortened by resynchronization. d. Sample-PointT
38、he Sample-Point is the point of time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. Copyright SAE International Provided by IHS under license with SAE Not for ResaleNo reproduction or networking permitted without license
39、from IHS -,- SAE J1939-11 Revised OCT1999 - 7 - 3.13Internal Delay TimeThe internal delay time of an ECU, tECU, is defined as the sum of all asynchronous delays that occur along the transmission and reception path of the individual ECUs, relative to the bit timing logic unit of the protocol IC. For
40、more details, see Figure 6. a.SynchronizationHard Synchronization and Resynchronization are the two forms of synchronization. They obey the following rules: 1.Only one Synchronization within one bit time is allowed. 2.An edge will be used for Synchronization only if the value detected at the previou
41、s Sample Point (previously read bus value) differs from the bus value immediately after the edge. 3.Hard Synchronization is performed during said edge whenever there is a recessive to dominant edge. 4.All other recessive to dominant edges fulfilling rules 1 and 2 will be used for Resynchronization w
42、ith the exception that a transmitter will not perform Resynchronization as a result of a recessive to dominant edge with a positive Phase Error if only recessive to dominant edges are used for Resynchronization. b.Synchronization Jump Width (SJW)As a result of Synchronization PHASE_SEG1 may be lengt
43、hened or PHASE_SEG2 may be shortened. The amount of lengthening or shortening of the Phase Buffer bit Segments has an upper bound given by the Synchronization Jump Width. The Synchronization Jump Width is less than or equal to PHASE_SEG1. Copyright SAE International Provided by IHS under license wit
44、h SAE Not for ResaleNo reproduction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 8 - FIGURE 6TIME RELATIONSHIP BETWEEN BIT TIMING LOGIC OF ECU A AND B DURING ARBITRATION Copyright SAE International Provided by IHS under license with SAE Not for ResaleNo reprodu
45、ction or networking permitted without license from IHS -,- SAE J1939-11 Revised OCT1999 - 9 - 3.14CAN Bit Timing RequirementsIt is necessary to ensure that a reliable network can be constructed with components from multiple suppliers. Without any bit timing restrictions, different devices may not be
46、 able to properly receive and interpret valid messages. Under certain network conditions it may also be possible for a particular device to have unfair access to the network. In addition, it makes network management (system diagnostics) much more difficult. CAN chip suppliers also recommend that all
47、 devices on a given network be programmed with the same bit timing values. (R)All CAN ICs divide the bit time into smaller sections defined as tq (time quantum). For most CAN ICs 1 tq = 250 ns (with a 16 MHz clock) (determined by oscillator frequency and baud rate prescaler). (R)Therefore specific v
48、alues for the bit timing registers need to be defined to ensure that a reliable network exists for all nodes based on the best tradeoffs between propagation delay and clock tolerance. Note that there are some differences in bit segment definition between manufacturers of CAN devices. (R)It is recomm
49、ended that a tq be selected which permits the sample point (see Figure 5) to be located as close to but not later than 7/8 of a bit time (0.875x4uS = 3.5uS). This provides the best tradeoff between propagation delay and clock tolerance. (R)The following values are recommended for typical controller ICs running at standard clock frequencies. At other frequencies, different values may h