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1、STDmEIA J-STD-OZb-ENGL 3999 3234b00 Ob43343 350 W JO/NT IMDUSTRY STAMDARD Semiconductor Design Standard for Flip Chip Applications I PC/EIA J-STD-026 AUGUST 1999 Copyright Telecommunications Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bern
2、ie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permitted without license from IHS -,-,- STDmEIA J-STD-02b-ENGL 1999 Notice EIA and IPC Standards and Publications are designed to serve the public inter- est through eliminating misunderstandings between manufacturers and pur-
3、chasers, facilitating interchangeability and improvement of prciducts, and assist- ing the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of EIA
4、 or IPC from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications pre- clude their voluntary use by those other than EIA or IPC members, whether the standard is to be used either domestically or internationall
5、y. Recommended Standards and Publications are adopted by EIA and IPC without regard to whether their adoption may involve patents on articles, materials, or processes. By such action, EIA and IPC do not assume any liability to any patent owner, nor do they assume any obligation whatever to parties a
6、dopting the Recommended Standard or Publication. Users are also wholly respon- sible for protecting themselves against all claims of liabilities for patent infringement. For Technical information Contact: Electronic Industries Alliance I PC Engineering Department 2215 Sanders Road 2500 Wilson Boulev
7、ard Arlington, VA 22201 Northbrook, IL 60062-6 135 Phone (847) 509-9700 Phone (703) 907-7500 F x (703) 907-7501 Fax (847) 509-9798 Please use the Standard Improvement Form shown at the end of this document. Copyright 1999. The Electronics Industries Alliance, Arlington, Virginia, and IPC, Northbrook
8、, Illinois. All rights reserved under both international and Pan-American copyright conventions. Any copyhg, scanning or ofher feproduchon of these materials without the prior wMen consent of the copyright holder rS strictly prohibited and wnstitutes infringement under the Copyright Law of the Unite
9、d States, Copyright Telecommunications Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permitted without license from IHS -,-,- IPC/EIA J-STD-026 ASSOCIATION CONNEC TI
10、NG r EL ECTRONICS INDUS TRIES Semiconductor Design Standard for Flip Chip Applications About This Document This document is intended to report on the work being done by several organizations concerned with the design of bare die in flip chip or chip scale configurations. Details were developed by co
11、mpanies who have implemented the processes described herein and have agreed to share their experiences. Readers are encouraged to communicate to the appropriate trade associations or societies any comments or obser- vations regarding details published in this document, or ideas for additional detail
12、s that would serve the industry. Users of this standard are encouraged to participate in the development of future revisions. Contact: EIA Engineering Department 2500 Wilson Boulevard Arlington, VA 22201 Phone (703) 907-7500 Fax (703) 907-7501 IPC 2215 Sanders Road Northbrook, IL 60062-6 I35 Phone (
13、847) 509-9700 Fax (847) 509-9798 Copyright Telecommunications Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permitted without license from IHS -,-,- IPC/EIA J-STD-O2
14、6 August 1999 Acknowledgment Members of the EIA Soldering Technology Committee (STC) and the IPC Device Manufacturers Interface Committee (A- I O) have worked together to develop this document. We would like to thank them for their dedication to this effort. Any Standard involving a complex technolo
15、gy draws mate- rial from a vast number of sources. While the principal members of the Flip Chip Task Group are shown below, it is not possible to include all of those who asisted in the evolution of this Standard. To each of them, the members of the EIA and IPC extend their gratitude. Device Manufac
16、turers Interface Committee Flip Chip Task Group Chair Chair Ray Prasad Keith DeHaven R. Prasad Consultancy Group Motorola EIA Soldering Technology Com mittee Chair Mark Kwoka Harris Semiconductor Flip Chip Task Group J. Mark Bird, Amkor Technology Syed Sajid Ahmad, Micron Bernie Aronson, EIA Pamela
17、Ashcraft, Delphi Delco Dieter Bergman, IPC Mike Brownell, Intel Dick Carpenter, IBM Keith DeHaven, Motorola Robert K. Doot, Motorola Werner Engelmaier, Engelmaier Technology Electronics Systems Associates Marty Freedman, AMP, Inc. Joe Fjelstad, Tessera Kuan-Shar Lei, Compaq Helen M. Low, Celestica R
18、ob Lyn, Celestica (IBM Canada Sub .) Susan Mack, Delphi Delco Electronics Systems Paul A. Magill, MCNC Phil Marcou, Chip Scale Inc. Tze W. Poon, Sematech Glenn Rinne, MCNC Ray Rinne, IBM Paul Totta, IBM East Fishkill Iwona Turlik, Motorola Dan Ward, Delphi Delco Electronics James Rausch, Delphi Delc
19、o Rod Frantz, Delphi Delco Electronics Systems Electronics Systems Systems Copyright Telecommunications Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permitted witho
20、ut license from IHS -,-,- IPC/EIA J-STD-O26 Auqust 1999 Table of Contents 1 SCOPE . 1 1 .I Purpose . I 1.2 Classifications . 1 1.2. I Bump Process Technologies I . 2.2 Substrate Technologies . 1 I . 2.3 I . 2.4 I . 3 Application Classes 1 Producibility Level 1 I . 4 Interpretation 2 Organization of
21、Design Information . 2 Order of Precedence . 2 Presentation 2 1.5 1.6 2 APPLICABLE DOCUMENTS 3 3 DESIGN CONSIDERATIONS . 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.5.1 3.5.2 3.5.2. I 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.6 3.7 3.8 3.9 3.9. I 3.9.1. I Terms and Definitions 3 General
22、. 3 Footprint Design 3 Electrical Considerations 6 Interconnect Parasitics . 6 Power and Ground Bumps 6 Redistribution Effects 8 Electromagnetic Radiation . 9 Electrical Bias Created by Non-Electrical Phenomena . 10 Reliability Considerations 1 O General . IO Thennai Fatigue . IO Distance to Neutral
23、 Point (DNP) IO Electromigration . 1 1 Thermomigration 1 I Metal Migration . 1 I Corrosion 11 Thermal Shock Resistance . I I Creep I 1 Alpha Particle Sensitivities Il Thermal Considerations . 13 Application Considerations I3 Test and Known Good Die Considerations 15 Process Descriptions . 15 Process
24、 A - Evaporation 15 Design 15 Process A - Bump Placement and Pad 3.9.1.2 Process A - Passivation . 17 3.9.1.3 Process A - Wafer Diameter and Thickness . 17 3.9. I . 4 3.9.1.5 3.9.2 3.9.2.1 3.9.2.2 3.9.2.3 3.9.2.4 3.9.2.5 3.9.3 3.9.3.1 3.9.3.2 3.9.3.3 3.9.3.4 3.9.3.5 3.9.4 3.9.5 3.9.6 3.10 3.11 3.11.
25、1 3.12 Process A . Fiducials and Test Structures i7 Process A . Die Edge and Scribe Streets . 18 Process B . Solder Paste Deposition 18 Process B . Bump Placement and Pad Design 18 Process B - Passivation . 19 Process B -Wafer Diameter and Thickness 20 Process B - Fiducials and Test Structures 20 Pr
26、ocess B - Die Edge and Scribe Streets . 22 Process C - Electroplated Tin-Lead Solder 23 Process C - Bump Placement and Pad Design 23 Process C - Passivation . 23 Process C -Wafer Diameter and Thickness 25 Process C - Fiduciais and Test Structures 25 Process C - Die Edge and Scribe Streets . 25 Proce
27、ss D - Gold Stud Bumping (under consideration) 25 Process E - Conductive Epoxy (under consideration) 25 Process F - Electroless Nickel with Solder Paste Deposition 25 Design Rules 26 Design Rule 1 26 Design Rule 2 26 Design Rule 3 26 Design Rule 4 26 Design Rule 5 27 Design Rule 6 27 Design Rule 7 2
28、7 Design Rule 8 27 Design Rule 9 28 Design Rule 10 28 Design Rule 11 29 Design Rule 12 29 Design Rule 13 29 Design Rule 14 31 Design Rule 15 31 Design Rule 16 31 Design Layout i Methods . 32 Data Format . 32 Documentation . 32 4 QUALITY ASSESSMENTS 33 4.1 Design . 33 . 111 Copyright Telecommunicatio
29、ns Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permitted without license from IHS -,-,- 4.1.1 4.1.2 4.2 4.2.1 4.2. I . 1 4.2.1.2 4.2.1.3 4.2.2 4.2.3 4.3 4.3.1 4.3.
30、2 4.3.3 Annex A Annex Annex C Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Design Review . 33 Design Rule Check on IC Layout . 33 Simula ti on 33 Electrical Analysis . 33 On-
31、Chip Crosstalk Simulations . 33 Driver and Receiver Models for System Simulation 33 Suggested Guidelines for Elecmcal Analysis and Simulation . 33 Thermal Analysis . 33 Mechanical Analysis: FEM . 33 Test Chip . 33 Test Chip Design . 33 Thermal Performance 34 Reliability . 34 . . . Normative Terminol
32、ogy and Acronyms 35 Acronyms . 37 Reference Information 39 Figures Peripheral Footprint Design . 4 Staggered Row and Fanout Constrained Footprint Design . 4 Universal Die Footprint Design 5 Wire Bond Connections Versus Array Bump Connections . 6 Bump Parasitics . 7 Nested I/O Footprint . 8 Central P
33、ower and Ground Footprint . 8 Redistribution of Peripheral to Area Array . 9 Distance to Neutral Point . 11 Alpha Particle Emission Track and UH Pairs 12 Distortion of Depletion by Alpha Partides 12 Chip Underfill Example . 14 Approximate Thermal Model for Flip Chip with Underfill . 14 Chip Thermal
34、Paste and Lid for Heat Sink Attach . 14 Simple Thermal Model for Flip Chip with Lid . 15 Evaporated Bump After Reflow 16 Evaporated Bump Before Reflow . 16 Evaporated Via Stnicture . 17 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figu
35、re 30 Figure 31 Figure 32 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Evaporated Via Requirements . 18 CMA Key for Evaporation Process 19 CMA Location for Evaporation Process . 20 Layout of Solder Paste Deposition (FOC) Bump Pad . IC Solder Past
36、e Deposition Bump Sputtered UBM Ater Reflow Alignment Key Dimensions - Solder Paste Deposition . Alignment Key Structure After Sputtered UBM - Solder Paste Deposition 22 Wafer Alignment Key Placement for the Solder Paste Deposition Process. Solder Paste Deposition Standard Bump Resistance and Shear
37、Pattern Layout Cross Section of UBM with Optional Passivation Layer Included 24 Electroplated Solder Bump Cross Section with Thin Film UBM Ater Reflow 25 Bump to Edge Seal Dimensions and Bump to Vision Key 30 Chip Edge Seal 30 Underlying Via Placement 31 Tables Representative Realistic Worst Case Us
38、e Environments for Surface Mounted Electronics and Recommended Accelerated Testing for Surface Mount Attachments 2 Typical Bump Parasitics Common Material Coefficients of Thermal Expansion . 10 Alpha Particle Emission of Semiconductor . 13 Standard Alignment Key Placement Positions . 23 Resistance a
39、nd Shear Test Pattern Dimensions . 24 Array and Peripheral Layout Guidelines for Process A - Evaporation 27 Peripheral Layout Guidelines for Solder Paste Deposition 28 Array Layout Guidelines for Solder Paste Deposition . 28 Bumps Per Die Area 28 Evaporated Bump to Chip Edge Minimum Pitch 29 Center
40、of Bump to Center of Scribe Street Rules for Solder Paste Deposition Process . 31 iv Copyright Telecommunications Industry Association Provided by IHS under license with EIALicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/29/2007 20:52:00 MDTNo reproduction or networking permi
41、tted without license from IHS -,-,- STD-EIA -STD-026-ENGL L999 3234b00 Ob43349 839 m August 1999 IPC/EIA J-STD-O26 Semiconductor Design Standard for Flip Chip Applications 1 SCOPE This standard addresses semiconductor chip design. It is intended for applications utilizing standard substrates, materi
42、ais, assembly, and test methods as well as established semiconductor fabrication and bumping processes. 1.1 Purpose The purpose is to provide flip chip design standards which are commensurate with established fabrication, bump, test, assembly, handling and application practices. Addressed are electr
43、ical, thermal, and mechanical chip design parameters and methodologies as well as the reliability associated with these items. These standards are intended for new designs as well as modifications of non-flip chip designs. 1.2 Cbssications 1.2.1 Bump Process Technologies The following processes for
44、forming bumps on semiconductor die intended for flip chip mounting have proven effective. Some are in full production, others are in development. (A) Evaporation (tin-lead) (B) Solder Paste Deposition (C) Electroplated Tin Lead (D) Gold Stud Bumping (E) Conductive Epoxy (F) Electroless Nickel Design
45、 rules for process technologies A, B and C are well-defined and are detailed in this standard; future revisions will incorporate those niles for the other processes listed as they become available. 1.2.2 Substrate Technologies bare die. These pertain primarily to the precision capability, pitch of b
46、onding site locations, and CTE characteristics. (W) Organic (Rigid) (see IPC-2222 and IPC-6012) (X) Flex (Flexible Organic) (see IPC-2223 and IPC-6013) (Y) Ceramic (Z) Silicon Four typical mounting structure technologies are listed and affect the design d e s of the 1.2.3 Application Classes The rel
47、iability of flip chip assemblies will be determined by design decisions. Assumptions are made for each design as to how long it has to survive and in what environment the product will be deployed. In addition, many companies have to determine what is an acceptable failure probability. Table 1 shows
48、the worst case anticipated use thermal environment for nine specific categories. Information is provided on their minimum and maximum temperature excursion, as well as the deita of which the equipment usually sees. Other information provides the details for the cycle time hours, cycles per year, and
49、 the years of service expected by the customer. Table 1 also indicates levels of accelerated tem- perature testing which might correspond to these environments. Accelerated testing is generally applied in electronics to examine product robustness to anticipated environmental exposures. Common methods include, but should not