《电子专业毕业设计（论文）外文翻译.doc》由会员分享，可在线阅读，更多相关《电子专业毕业设计（论文）外文翻译.doc（20页珍藏版）》请在三一文库上搜索。
1、英文资料及中文翻译 The Design of a Rapid Prototype Platform for ARM Based Embedded SystemHardware prototype is a vital step in the embedded system design. In this paper, we discuss our design of a fast prototyping platform for ARM based embedded systems, providing a low-cost solution to meet the request of f
2、lexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to em
3、bedded system of other types. I.INTRODUCTIONEmbedded systems are found everywhere, including in cellular telephones, pagers, VCRs, camcorders, thermostats, curbside rental-car check-in devices, automated supermarket stockers, computerized inventory control devices, digital thermometers, telephone an
4、swering machines, printers, portable video games, TV set-top boxes - the list goes on. Demand for embedded system is large, and is growing rapidly. In order to deliver correct-the-first-time products with complex system requirements and time-to-market pressure, design verification is vital in the em
5、bedded system design process. A possible choice for verification is to simulate the system being designed. If a high-level model for the system is used, simulation is fast but may not be accurate enough, with a low-level model too much time may be required to achieve the desired level of confidence
6、in the quality of the evaluation. Since debugging of real systems has to take into account the behavior of the target system as well as its environment, runtime information is extremely important. Therefore, static analysis with simulation methods is too slow and not sufficient. And simulation canno
7、t reveal deep issues in real physical system. A hardware prototype is a faithful representation of the final design, guarantying its real-time behavior. And it is also the basic tool to find deep bugs in the hardware. For these reasons, it has become a crucial step in the whole design flow. Traditio
8、nally, a prototype is designed similarly to the target system with all the connections fixed on the PCB (printed circuit boards).As embedded systems are getting more complex, the needs for thorough testing become increasingly important. Advances in surface-mount packaging and multiple-layer PCB fabr
9、ication have resulted in smaller boards and more compact layout, making traditional test methods, e.g., external test probes and bed-of-nails test fixtures, harder to implement. As a result, acquiring signals on boards, which is beneficial to hardware testing and software development, becomes infeas
10、ible, and tracking bugs in prototype becomes increasingly difficult. Thus the prototype design has to take account of testability. However, simply adding some test points is not enough. If errors on the prototype are detected, such as misconnections of signals, it could be impossible to correct them
11、 on the multiple-layer PCB board with all the components mounted. All these would lead to another round of prototype fabrication, making development time extend and cost increase.Besides testability, it is important to maintain high flexibility during development of the prototype as design specifica
12、tion changes are common. Nowadays complex systems are often not built from scratch but are assembled by reusing previously designed modules or off-the-shelf components such as processors, memories or peripheral circuitry in order to cope with more aggressive time-to-market constraints. Following the
13、 top-down design methodology, lots of effort in the design process is spent on decomposing the customers, requirements into proper functional modules and interfacing them to compose the target system.Some previous research works have suggested that FPLDs (field programmable logic device) could be ad
14、ded to the final design to provide flexibility as FPLDs can offer programmable interconnections among their pins and many more advantages. However, extra devices may increase production cost and power dissipation, weakening the market competition power of the target system. To address these problems
15、, there are also suggestions that FPLDs could be used in hardware prototype as an intermediate approach 1-3, whereas this would still bring much additional work to the prototype design. Moreover, modules on the prototype cannot be reused directly. In industry, there have been companies that provide
16、commercial solutions based on FPLDs for rapid prototyping 4. Their products are aimed at SOC (system on a chip) functional verification instead of embedded system design and development.In this paper, we discuss our design of a Rapid Prototyping Platform for ARM based Embedded System, providing a lo
17、w cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. The rest of the paper is organized as follows. In section 2, we discuss the details
18、of our rapid prototyping platform. Section 3 shows the experimental results, followed by an overall conclusion in section 4.II. THE DESIGN OF A RAPID PROTOTYPING PLATFORMA. OverviewARM based embedded processors are wildly used in embedded systems due to their low-cost, low-power consumption and high
19、 performance. An ARM based embedded processor is a highly integrated SOC including an ARM core with a variety of different system peripherals5. Many arm based embedded processors, e.g.6-8, adopt a similar architecture as the one shown in Fig. 1.The integrated memory controller provides an external m
20、emory bus interface supporting various memory chips and various operation modes (synchronous, asynchronous, burst modes). It is also possible to connect bus-extended peripheral chips to the memory bus. The on-chip peripherals may include interrupt controller, OS timer, UART, I2C, PWM, AC97, and etc.
21、 Some of these peripherals signals are multiplexed with general-purpose digital I/O pins to provide flexibility to user while other on-chip peripherals, e.g. USB host/client, may have dedicated peripheral signal pins. By connecting or extending these pins, user may use these onchip peripherals. When
22、 the on-chip peripherals cannot fulfill the requirement of the target system, extra peripheral chips have to be extended.The architecture of an ARM based embedded system is shown in Fig. 2. The whole system is composed of embedded processor, memory devices, and peripheral devices. To enable rapid pr
23、ototyping, the platform should be capable of quickly assembling parts of the system into a whole through flexible interconnection. Our basic idea is to insert a reconfigurable interconnection module composed by FPLD into the system to provide adjustable connections between signals, and to provide te
24、stability as well. To determine where to place this module, we first analyze the architecture of the system.The embedded system shown in Fig. 2 can be divided into two parts. One is the minimal system composed of the embedded processor and memory devices. The other is made up of peripheral devices e
25、xtended directly from on-chip peripheral interfaces of the embedded processor, and specific peripheral chips and circuits extended by the bus.The minimal system is the core of the embedded system, determining its processing capacity. The embedded processors are now routinely available at clock speed
26、s of up to 400MHz, and will climb still further. The speed of the bus connecting the processor and the memory chips is exceeding 100MHz. As pin-to-pin propagation delay of a FPLD is in the magnitude of a few nanoseconds, inserting such a device will greatly impair the system performance.The peripher
27、als enable the embedded system to communicate and interactive with the circumstance in the real world. In general, peripheral circuits are highly modularized and independent to each other, and there are hardly needs for flexible connections between them.Here we apply a reconfigurable interconnection
28、 module to substitute the connections between microcomputer and the peripherals, which enables flexible adjusting of connections to facilitate interfacing extended peripheral circuits and modules. As the speed of the data communication between the peripherals and the processor is much slower than th
29、at in the minimal system, the FPLD solution is feasible.Following this idea, we design the Rapid Prototyping Platform as shown in Fig. 3. We define the interface ICB between the platform and the embedded processor core boar that holds the minimal system of the target embedded system. The interface I
30、PB between the platform and peripheral boards that hold extended peripheral circuits and modules is also defined. These enable us to develop different parts of the target embedded system concurrently and to compose them into a prototype rapidly, and encourage module reusing as well. The two interfac
31、es are connected by a reconfigurable interconnect module. There are also some commonly used peripheral modules, e.g. RS232 transceiver module, bus extended Ethernet module, AC97 codec, PCMCIA/CompactFlash Card slot, and etc, on the platform which can be interfaced through the reconfigurable intercon
32、nect module to expedite the embedded system development.B. Reconfigurable Interconnect ModuleWith the facility of state-of-arts FPLDs, we design a reconfigure interconnection module to interconnect, monitor and test the bus and I/O signals between the minimal system and peripherals.As the bus access
33、ing obeys specific protocol and has control signals to identify the data direction, the interconnection of the bus can be easily realized by designing a corresponding bus transceiver into the FPLD, whereas the interconnection of the I/Os is more complex. As I/Os are multiplexed with on-chip peripher
34、als signals, there may be I/Os with bi-direction signals, e.g. the signals for on-chip I2C9 interface, or signals for on-chip MMC (Multi Media Card10) interface. The data direction on these pins may alter without an external indication, making it difficult to connect them via a FPLD. One possible so
35、lution is to design a complex state machine according to corresponding accessing protocol to control the data transfer direction. In our design we assign specific locations on the ICB and IPB interfaces to these bi-direction signals and use some jumpers to directly connect these signals when needed.
36、 The problem is circumvented at the expense of losing some flexibility.The use of FPLD to build the interconnection module not only offers low cost and simple architecture for fast prototyping, but also provides many more advantages. First, interconnections can be changed dynamically through interna
37、l logic modification and pin re-assignment to the FPLD. Second, as FPLD is connected with most pins from the embedded processor, it is feasible to detect interconnection problems due to design or physical fabricate fault in the minimal system with BST (Boundary-Scan Test, IEEE Standard 1149.1 specif
38、ication). Third, it is possible to route the FPLD internal signals and data to the FPLDs I/O pins for quick and easy access without affecting the whole system design and performance. It is even possible to implement an embedded logical analyzer into the FPLD to smooth the progress of the hardware ve
39、rification and software development.C. Power SupplyPower dissipation has a great impact on system cost and reliability. It is an increasingly important problem in embedded systems designs not only for the portableelectronics industry but in other areas including consumer electronics, industry contro
40、l, communications, etc. In order to facilitate the design of power supply for the target embedded system, power supply issues have also been considered in the design of the platform.First, the power supplies to the devices on the platform are separated from those to the core board and peripheral exp
41、and boards, which makes it more realistic to measure and verify the power dissipation on the platform for the target embedded system. Second, the power supplies for the core board and peripheral expand boards are built on a separate board and connected to the platform through a slot. As a result, it
42、 provides flexibility for power system design while speeding up the whole design process.To meet the demand for higher system speed and lower power consumption in data communications and processing, embedded processor vendors use increasingly advanced processing technologies requiring lower core ope
43、rating voltages, and keep the interface voltage compatible with most low voltage semiconductor devices on market. Consequently, almost every embedded processor requires more than one power supply, such as power supply for internal logic, for PLLs and oscillators, for memory bus interface, and for ot
44、her I/Os. Further, different embedded processors may have different requirements on power supply, such as different power supply voltage, power-up sequence, and different strategies to adjust the core voltage in different CPU run mode for minimizing power dissipation.A survey of some widely used ARM
45、 based embedded processor suggests that most of them need no more than 3 groups of separated power supply, as shown in Table 1. As the peripherals may require different supply voltages for special purpose, such as +5V for powering the USB ports, we divide the power supply from the power supply slot
46、into 4 separated channels, which is connected to both the core board slot and the peripheral board slot. Each channel of power supplies has a “power good” signal to indicate power output status of the channel, and a shutdown signal to shut the power supply of the channel down. And these signals are
47、directly connected to the core board slot to accommodate the embedded processors requirement of power-up sequence. In order to enable dynamic voltage adjusting, some control signals are routed to the power supply board by the reconfigurable interconnect module.III. EXPERIMENTAL RESULTSAs the Rapid P
48、rototyping Platform is still under development, we present an example applied with the same considerations in the Rapid Prototyping Platform. It is an embedded system prototype based on Intel XScale PXA255, which is an ARM based embedded processor. The diagram of the prototype is illustrated in Fig.
49、 5(a). The photo is shown in Fig. 5(b), where a Bluetooth module is connected to the prototype USB port and a CF LAN card is inserted.The FPGA (an Altera Cyclone EP1C6F256) here offers the same function as the reconfigurable interconnection module shown in Fig. 3. Most of the peripheral devices are expanded to the system through the FPGA, and more peripherals can be easily interfaced when needed. As both of the FPGA and PXA255 support the BST, we can detect faults, e.g. short-circu