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1、个人资料整理仅限学习 使用 - 1 - / 10 本 科 生 毕 业 论 文 One microprocessor of 8 (CPU. ( 2 At slice data memory RAM (128B/256B,it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3 Procedure memory ROM/EPROM (4KB/8KB , is used t
2、o preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc ( 4 Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5 Two timer / counter, each
3、 timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6 Five cut off cutting off the control system of the source . ( 7 One all duplexing serial
4、 I/O mouth of UART (universal asynchronous receiver/transmitter (UART , is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8 Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation f
5、requency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and 个人资料整理仅限学习 使用 3 / 10 controller , etc T
6、he arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count
7、by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transm
8、ission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure cou
9、nter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers,
10、only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic b
11、eat, just like an orchestra according to the beat play that is commanded. p1EanqFDPw There are ROM (procedure memory , can only read and RAM in 8051 slices (data memory, can is it can write two to read, they have each independent memory address space, dispose way to be the same with general memory o
12、f computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporar
13、ily and the data are buffered etc In RAM of this 128B, 个人资料整理仅限学习 使用 4 / 10 there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the sam
14、e that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different addr
15、ess space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memo
16、ry space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called
17、 Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1 In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses. (2 The data memory address space outside one of 64KB, the address is arranged from 00
18、00H 64KB FFFFH (with 16 addresses too to the location. (3 Data memory address space of 256B (use 8 addresses. Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM
19、 order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.DXDiTa9E3d 8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be
20、used as introduction and exported independently. Each port includes a latch (namely special function register , 个人资料整理仅限学习 使用 5 / 10 one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these s
21、elf-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off。 P0 mouth is a two-way bus, send the introduction of 8 low addresses and
22、 data / export in timesharing RTCrpUDGiT The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip comput
23、er to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from o
24、ther mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should
25、 write “1“ to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two
26、effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approx
27、imate , can draw the pin to the high level fast 。 When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the 个人资料整理仅限学习 使用 6 / 10 resistance on
28、neednt answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The stru
29、cture of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have “and “ 3 door and 4 buffer“. Two part these, make her besides accur
30、ate two-way function with P1 mouth just, can also use the second function of every pin, “and “ door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 oclock, output Q end signal。 Act as Q =At 1 oclock, can output W line sig
31、nal . At the time of programming, it is that the first function is still the second function but neednt have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte to v
32、isit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth.5PCzVD7HxA Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output
33、. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain- source resistance is it urge to open a way, do not need to have the resistance of
34、 drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transi
35、stor to regard as, should contact a resistance among the port and transistor base , in 个人资料整理仅限学习 使用 7 / 10 order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to tur
36、n PC into 0000H initially , make the one- chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there arent mistake, in order to extricate oneself from a predicam
37、ent , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles the above its effective times. I
38、f 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:jLBHrnAILg Restore to the throne the circuit and include
39、 two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST hand over to Schmitts trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to
40、the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the thr
41、one in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop ones head and monitor the pin with the oscillograph tentatively, push and is restored to the thro
42、ne the key, the wave form that observes and has enough range is exported (instantaneous, can also through is it restore to the throne circuit group holding value carry on the experiment to change. xHAQX74J0X 个人资料整理仅限学习 使用 8 / 10 MCS -51 系列单片机地功能和结构 MCS - 51 系列单片机具有一个单芯片电脑地结构和功能, 它是英特尔公 司生产地系列产品地名称.
43、这家公司在 1976 年推出后 , 引进 8 位单芯片地 MCS - 48 系列计算机后于 1980年推出地 8 位地 MCS - 51 系列单芯片计 算机. 诸如此类地单芯片电脑有很多种, 如 8051,8031,8751,80C51BH,80C31BH等, 其基本组成 , 基本性能和指令系统 都是相同地 . 8051 是 51系列单芯片电脑地代表 . 一个单芯片地 计算机系统由以下几个部分组成：1）一个 8 位地微处理器 CPU ）.2） 片内数据存储器 RAM128B/256B）, 它只读 / 写数据 , 如结果不在操作过程 中, 最终结果要显示数据 3）程序存储器 ROM/ EPROM
44、4KB/8KB）, 是用来 保存程序 , 一些初步地数据和切片地形式. 但一些单芯片电脑没有考虑ROM / EPROM, 如 8031,8032,80C51 等等.4）4 个 8 路运行地 I / O接 口,P0,P1,P2,P3, 每口可以用作入口 , 也可以用作出口 . 5 ）两个定时 / 计 数器, 每个定时 / 计数器可设置和计数地方式, 用来计数外部事件 , 可以设置 成定时方式也可以根据计算结果或定时控制实现计算机. 6 ）5 个中断 7）一个全双工串行地I / UART 通用异步接收器I 口/ 发送器 UART ）, 它是实现单芯片电脑或单芯片计算机和计算机地串行通信使用.8）振
45、荡 器和时钟产生电路 , 需要考虑石英晶体微调能力. 允许振荡频率为 12MHz, 每一个上述地部分都是通过内部数据总线连接. 其中 CPU 是一个芯片计算 机地核心 , 它是计算机地指挥中心 , 是由算术单元和控制器等部分组成. 算 术单元可以进行 8 位算术运算和逻辑运算 , ALU 单元是其中一种运算器,1 8 个存储设备 , 暂存设备地积累设备进行协调, 程序状态寄存器PSW 积累了 2 个输入端地计数等检查暂时作为一个操作往往由人来操作谁储存1 输入 地是它使操作去上暂时计数, 另有一个操作地结果 , 回环协调 . 此外, 协调往 往是作为对 8051 内地数据传输转运站考虑 . 作
46、为一般地微处理器 , 它是最 繁忙地 , 帮助记住和同意与其地顺序表示. 该控制器包括程序计数器 , 解密 地顺序 . 振荡器和定时电路等地程序计数器是一个由8 个计数器为 2, 总计 16 位. 这是一个字节地地址 , 其实程序计数器 , 是将在个人电脑内进行 . 从 而改变它地内容可以改变方向地程序进行. 在 8051 地单芯片电脑中地电路 , 只需要外部石英晶体和频率微调电容, 其频率范围为 1.2MHz地其 12MHz 地. 这种脉冲信号 , 作为 8051 地工作 , 即单位时间地最低基本节奏. 8051 是其 他电脑一样 , 在拍控制地基本工作在和谐, 就像一个管弦乐队 , 根据击
47、败发 挥是指挥 . 有光盘 程序存储器 , 只能读取） , 并在 8051 片数据存储 器 RAM, 可以是可写可读 , 他们各自独立地内存地址空间, 处理办法是 , 与一 般地电脑记忆体相同 . 8051 和 8751地程序存储器地存储容量4KB地程序 切片, 地址开始从 0000H开始执行 , 维护地程序和形式不断使用. 数据 8051 - 8751 地内存数据存储器128B条 8031,地址虚假 00FH,中层结果存入操 个人资料整理仅限学习 使用 9 / 10 作使用 , 数据存储和数据是暂时缓冲等. 在这 128B条内存 , 有 32 字节, 可 以作为工作寄存器使用 , 这和一般地
48、微处理器是不同地,8051 片 RAM 和登 记形成地同一级到安排地位置. 这不是很相同地 ,MCS - 51 系列内存地单 芯片计算机和通用计算机作主除了道路. 通用计算机地第一个地址空 间,ROM 和 RAM, 可安排在不同地空间在这个范围内地地址范围, 即 ROM 和 RAM 地址地形成与分布在不同地地址空间. 在访问内存 , 相应地 , 只有一个 地址地内存单元 , 可以用外部存储 , 也可以内存 , 并通过访问顺序与此类似 . 这种内存结构地一种被称为普林斯顿结构.8051 记忆分为程序存储器空间 和数据存储空间地物理结构上划分, 有四个在所有地记忆体空间：在1 和 数据外部数据存储
49、器和程序存储器空间之一, 一组在外面一个内存空间地 程序商店 , 结构这一种形式地程序和数据存储器器件数据存储器分开地形 式, 称为哈佛结构 . 但是, 从用户使用 ,8051 地内存地址空间分为三种：分 为1）片内 ,使用 16 个地址一致地 FFFFH, 地点为 0000H,块）. 2 ）64KB 地外部数据存储器空间地一个地址, 该地址是从 0000H开始执行 64KB地 FFFFH 安排 16地址, 也到该位置 . 3 ）数据存储器地 256B使用 8 个地 址）地地址空间 . 上述三个内存空间地地址重叠, 区分和设计地 8051指令 系统中不同地数据传输顺序代码：CPU 地访问片 , 访问 RAM 块顺序使用 MOVX 指令外片 , 内存为访问片 . 8051 单芯片地电脑有4 个 8 步行并 进地 I / O端口, 分别为 P0,P1,P2 和 P3.每个端口 8 位地双向口 , 共占了 32 针. 每一个 I / O线可作为独立地入口和出口. 每个端口包括一个锁存 器即特殊功能寄存器） ,1 名入口和 1 出口引进缓冲区 . 使数据能锁存输 出时, 数据缓冲区时 , 可以引进 , 但 4 个通道这些自我相同地功能. 系统中地 内存片展开外来地 , 这四个港口可作为准确地双向地I / 共同使用输出口 . 系统地内存中展开外来地片,P2 口处于高位