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1、ARM Assembly language programming,Agenda ARM Data processing instructions ARM Data transfer instructions Arm Control flow instructions Features of Thumb state,ARM uses three types of instructions Data processing instructions (arithmetic operations, logical operations, register moves , comparisons, s
2、hift operations). Data transfer (register load/store instructions). Control flow instructions (branch instructions).,Data processing instructions Rules apply to ARM data processing instructions : - All operands are 32 bit s , come either from registers or aas specified as constants in the instructio
3、n itself - The result is also 32 bits and is placed in a register. - 3 operands are used : 2 for inputs and 1 for result. Ex. : ADD r0,r1,r2 ; r0 = r1 + r2 Works for both unsigned and 2s complement signed numbers. This may produce carry out signal and overflow bits , but ignored by default Result re
4、gister can be same as an input operand register.,Data processing instructions (contd) ARMs basic arithmetic operations :,ADD r0,r1,r2 ; r0 = r1 + r2 ADC r0,r1,r2 ; r0 = r1 + r2 +C SUB r0,r1,r2 ; r0 = r1 r2 SBC r0,r1,r2 ; r0 = r1 r2 + c + 1 RSB r0,r1,r2 ; r0 = r2 r2 RSC r0,r1,r2 ; r0 = r2 r1 + c - 1,
5、RSB stands for reverse subtraction. Operands may be unsigned or 2s complement integers. C is the carry bit in the CPSR,Data processing instructions (contd) ARMs bit-wise logical operations :,AND r0,r1,r2 ; r0 = r1 and r2 ( bit-by-bit for 32 bits) ORR r0,r1,r2 ; r0 = r1 or r2 EOR r0,r1,r2 ; r0 r1 xor
6、 r2 BIC r0,r1,r2 ; r0 = r1 and not r2,BIC stands for bit clear, where every 1 in the second operand clears the corresponding bit in the first :,r1 : 0101 0011 1010 1111 1101 1010 0110 1011 r2 : 1111 1111 1111 1111 0000 0000 0000 0000 r0 : 0000 0000 0000 0000 1101 1010 0110 1011,Data processing instr
7、uctions (contd) ARMs register move operations :,MOV r0,r2 ; r0 = r2 MVN r0,r2 ; r0 = not r2,MVN stands for move negated :,r2: 0101 0011 1010 1111 1101 1010 0110 1011 r0 : 1010 1100 0101 0000 0010 0101 1001 0100,Data processing instructions (contd) ARMs register comparison operations :,CMP r1,r2 ; se
8、t cc on r1 r2 CMN r1,r2 ;set cc on r1 + r2 TST r1,r2 ; set cc on r1 and r2 TEQ r1,r2 ; set cc on r1 xor r2,results of subtract , add, and, xor are NOT stored in any registers The condition code bits ( cc) in the CPSR are set or cleared by these instructions Ex CMN r1,r2 : N = 1 if MSB of the additio
9、n ( r1 + r2 ) results in 1 else N = 0 Z = 1 if the result of the addition is zero , else Z = 0 C is set to the carry-out of the addition V is set to the overflow of the addition,Data processing instructions (contd) ARM has clever feature . In any data processing instructions, we can apply to the sec
10、ond register a shift operation For example:,ADD r3,r2,r2,LSL # 3,Here LSL means logical shift left by the specified number of bits. Note that this is still a single ARM instruction , executed in a single cycle In most processors , this is a separate instruction , while ARM integrates this shifting i
11、nto the ALU It is also possible to use a register value to specify the number of bits the second operand should be shifted by :,ADD r3,r2,r2,LSL r2,Data processing instructions (contd) Six possible ARM shift operations can be used,00000,00000,31,0,0,31,LSL # 5,LSR # 5,LSL : fill the vacated bits at
12、the least significant end of the word with zeros. LSR : fill the vacated bits at the most significant end of the word with zeros.,Data processing instructions (contd) ASL : this is the same as LSK. ASR : fill the vacated bits at the most significant end of the word with zeros if the source operand w
13、as positive , and with ones it is negative.,0,1,11111 1,00000 0,31,0,0,31,ASR # 5 , positive operand,ASR # 5 , negative operand,Data processing instructions (contd) ROR : the bits which fall off the least significant end are used to fill the vacated bits at the most significant end of the word. RRX
14、: rotate right extended by 1 place : the vacated bit ( bit 31) is filled with the old value of the C flag and the operand is shifted one place to the right. This is effectively a 33 bit rotating using the register and the C flag,31,0,0,31,ROR # 5,RRX,C,C,Data processing instructions (contd) ARM has
15、a number of multiply instructions : - produce the product of two 32-bit binary numbers held in the registers. - result of 32-bit by 32-bit is 64 bits ,. The entire 64-bit result is stored in two registers. Sometimes only 32 bits of the product are saved - Multiply Accumulate instruction also adds th
16、e product to a running total.,MUL r4,r3,r2 ; r4 = r3 * r2 MLA r4,r3,r2,r1 ; r4 = ( r3 * r2 ) + 1,Difference from the other arithmetic operations : - immediate second operands are not supported - the result register cannot be the same as the second source register.,ARM DATA transfer instructions 3 ba
17、sic forms of data transfer instructions : - single register load / store instructions. - Multiple register load / sore instructions - single register swap instruction ( combined lad and sore) Use a value in one register ( called the base register ) as a memory address and either loads the data value
18、 from that address into a designation register or stores the register value to memory : LDR r0,r1 ; r0 = mem32r1 STR r0,r1 ; mem32r1 = r0 This is called register-indirect addressing,ARM DATA transfer instructions (contd) to load or store from or to a memory locations , an ARM register must be initia
19、lized to contain the address of that location. In order to do that a pseudo instruction is used : ADR ( the assembler translate it to a real data processing instruction) Ex. Copy of data within memory TABLE1 to TABLE2,Copy ADR r1, TABLE1 ADR r2,TABLE2 LDR r0,r1 STR r0,r2 TABLE1 TABLE2.,ARM DATA tran
20、sfer instructions (contd) Extend the copy program further to copy the next word :,Copy ADR r1, TABLE1 ADR r2,TABLE2 LDR r0,r1 STR r0,r2 ADD r1,r1, # 4 ADD r2,r2, # 4 TABLE1 TABLE2.,Simplify with pre-indexed addressing mode : LDR r0, r1 ,# 4 ; r0 = mem32 r1 + 4 ,Base address,offset,Effective address,
21、ARM DATA transfer instructions (contd) pre-indexed addressing does not change r1. Sometimes , it is useful to modify the base register to point to the new address . This is achieved by adding a ! , and we then have auto-indexing : LDR r0,r1, # 4 ! ; r0 = mem31 r1 + 4 ; r1 = r1 + 4 The ! indicates th
22、at the instruction should update the base register after the data transfer. In post-indexed addressing , the base address is used without an offset as the transfer address, after which it is always modified. Using this , we can improce the program mpre LDR r0 , r1, # 4 ; r0 = mem32r1 ; r1 = r1 + 4,C
23、opy ADR r1, TABLE1 ADR r2,TABLE2 LDR r0,r1 , # 4 STR r0,r2 , # 4 TABLE1 TABLE2.,ARM DATA transfer instructions (contd),LDR and STR instructions are repeated until the required number of values has been copied into TABLE2 , and then the loop is exited,ARM DATA transfer instructions (contd),The size o
24、f the data item which is transferred may be a single 8-bit byte instead of a 32-bit word . This option is selected by adding a letter B onto the symbolic operation code :,LDRB ro, r1 ; r0 = mem8 r1 ,LDR and STR instructions only load/store a single 32-bit word,ARM DATA transfer instructions (contd)
25、Multiple register data transfers ARM can load/store any subset of its register in a single instruction by using load/store multiple instructions . For example :,LDMIA r1, r0,r2,r4 ; r0 = mem32r1 ; r2 = mem32r1 + 4 ; r4 = mem32r1 + 8,Base_addr,r0,r1,r2,r3,r4,Base_addr,Base_addr + 8,Base_addr + 4,Memo
26、ry,STMIA r1, r0,r2,r4,Base register r1 has not been changed,ARM DATA transfer instructions (contd) We can update the vase register by adding ! after it :,LDMIA r1 ! , r2 - r9 ; r2 = mem32r1 ; ; r9 = mem32r1 + 28 ; r1 = r1 + 32,Load multiple,Increment base address,Update r1 After use,Base address is
27、incremented after it is used,Load registers r2 to r9,ARM DATA transfer instructions (contd) Example of moving 8 bytes from a source memory location to a destination memory location,ADR r0, src_addr ; initialize src_addr ADR r1, deat_addr ; initialize dest_addr LDMIA r0! , r2 r9 ; fetch 8 words from
28、memory ; and update r0 = r0 + 32 STMIA r1 , r2 r9 ; copy 8 words to mem, r1 unchanged,When using LDMIA and STMIA instructions we ; 1. increment the address in memory to load/store our data 2. The increment of the address occurs AFTER the address is used. Four different forms of load /store instructi
29、ons are available : increment After LDMIA and STMIA increment Before LDMIB and STMIB decrement After LDMDA and STMDA decrement Before LDMDB and STMDB,ARM DATA transfer instructions (contd) Multiple register transfer addressing modes,r9,r9,r9,r9,STMIA r9! , r0,r1,r5,STMIB r9! , r0,r1,r5,&1000,&100c,&
30、1018,&1018,&100c,&1000,ARM DATA transfer instructions (contd) Multiple register transfer addressing modes,r9,r9,r9,r9,STMDA r9! , r0,r1,r5,STMDB r9! , r0,r1,r5,&1000,&100c,&1018,&1018,&100c,&1000,ARM DATA transfer instructions (contd) Stack addressing A stack is last-in-first-out which supports dyna
31、mic memory allocation, that is , memory allocation where the address to store a data value is not known at the time the program is compiled. A stack is usually implemented as a linear structure which grows up ( an ascending stack) or down ( a descending stack) memory as data is added to it and shrin
32、ks back as the data is removed . A stack pointer holds the current top of the stack , either by 1. pointing to the last valid data item pushed onto the stack ( a full stack) or 2. by pointing to vacant slot where the next data item will be placed ( an empty stack) ARM multiple register transfer inst
33、ructions supports all four forms of stack,ARM DATA transfer instructions (contd) Stack addressing Full ascending : the stack grows up through increasing memory addresses and base register points to the highest address containing a valid item,r9,r9,STMFA r9! , r0,r1,r5,&1018,&100c,&1000,ARM DATA tran
34、sfer instructions (contd) Stack addressing Empty ascending : the stack grows up through increasing memory addresses and base register points to the first empty location above the stack,r9,r9,STMEA r9! , r0,r1,r5,&1000,&100c,&1018,ARM DATA transfer instructions (contd) Stack addressing Full descendin
35、g : the stack grows down through decreasing memory addresses and base register points to the lowest address containing a valid item,r9,r9,STMFD r9! , r0,r1,r5,&1018,&100c,&1000,ARM DATA transfer instructions (contd) Stack addressing Empty descending : the stack grows down through decreasing memory a
36、ddresses and base register points to the first empty location below the stack,r9,r9,STMED r9! , r0,r1,r5,&1000,&100c,&1018,ARM DATA transfer instructions (contd) Swap Instruction The swap instruction is a special case of load instruction It swaps the content of memory with the contents of a register
37、 Example,pre Mem320x8000 = 0x12345678 r0 = 0x00000000 , r1 = 0x11112222 , r2 = 0x00008000 Swp r0,r1, r2 post Mem320x8000 = 0x11112222 r0 = 0x12345678 , r1 = 0x11112222 , r2 = 0x00008000,Control flow Instructions (contd) The basic branch instruction is :,B Label ; unconditionally branch to Label Labe
38、l .,Conditionally branched instructions can be used to control loops :,MOV r0, #10 ;initialize loop counter r0 Loop SUB r0,r0, #1 ; decrement loop counter CMP r0, #0 ; is it zero ? BNE loop ; repeat,Control flow Instructions (contd) ARM Branch instructions,Control flow Instructions (contd) Condition
39、al execution Conditional execution allies not only to branches , but to all ARM instructions For Example,CMP r0,#5 ; if (r0 != 5 then BEQ BYPASS ADD r1,r1,r0 SUB r1,r2,r2 BYPASS .,Can be replaced by a smaller and faster sequence:,CMP r0,#5 ; if (r0 != 5 then ADDNE r1,r1,r0 SUBNE r1,r2,r2 BYPASS .,He
40、re the ADDNE and SUBNE instruction are executed only if Z = 0 i.e. CMP instruction gives non-zero result,Control flow Instructions (contd) Branch and Link instructions A common requirement in a program is to be able to branch to a subroutine and resume the original code sequence when the subroutine
41、has completed. ARM offers this functionality through branch and link instruction which apart from branching to the subroutine , also saves the address of the instruction following the branch in the link register ,r14. Example:,BL SUBR ; branch to SUBR ; return to here SUBR ; subroutine entry point M
42、OV pc, r14 ; return,Control flow Instructions (contd) Branch and Link instructions A subroutine that calls another subroutine should first save r14 before calling the subroutine , otherwise the new return address will override the old one and it will not be possible to find the way back to the origi
43、nal caller The normal mechanism used can be to push r14 onto a stack and restore it back when required.,BL SUB1 SUB1 STMFD r13! , ro- r2, r14 ; save work and link register BL SUB2 LDMFD r13!, r0-r2 , r14 ; restore work regs and return SUB2 MOV pc, r14 ; copy r14 into r15 to return,Control flow Instr
44、uctions (contd) Supervisor calls SWI software interrupt instruction Forces execution to jump to the vector address 0x00000008, from where then further jumps to ISR The supervisor provides trusted way to access system resources which appear to the user-level program rather like special subroutine acc
45、esses. SWI instruction can be used to call these functions.,Thumb instruction set Features of Thumb state All Thumb instructions are 16 bits in length Thumb has higher code density the space taken by an executable program - than ARM . On average a Thumb implementation of the same code takes up aroun
46、d 30% less memory than equivalent ARM implementation. Most code written for Thumb is in high-level language such as C and C+. Each Thumb instruction is related to a 32-bit ARM instruction.,Decoder,ADD ro, # 3,ADDS ro, ,ro, # 3,Thumb 16-bit instruction,ARM 32-bit instruction,Thumb instruction decodin
47、g,Thumb instruction set Features of Thumb state (contd) In Thumb only the low registers r0 to r7 are fully accessible. The higher registers r8 to r12 are only accessible with MOV , ADD , or CMP instructions. In thumb only the branch instructions are conditionally executed. The barrel shifter operati
48、ons are separate instructions The Thumb mode includes POP and PUSH instructions as stack operations. These instructions only support a full descending stack. There are no Thumb instructions to access the coprocessors, cpsr and spsr. If any interrupt or exception flag is raised in Thumb state, the processor automatically reverts back to ARM state to handle the exception ARM-Thumb interworking is the name given to the method of linking ARM and the Thumb code together for both assembly and C/C+. It handles the transition between the two states.,