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1、 2683BATARM03-10-03 Interrupt Generation Using the AT91 Timer/Counter Introduction This application note describes how to generate an Interrupt by using the Timer/Counter (TC) in the AT91 series of microcontrollers. Timer/Counter Overview The AT91 series features a Timer/Counter block, which include
2、s three identical 16-bit timer counter channels. Each channel can be independently programmed, through its two operating modes, to perform a wide range of functions including frequency mea- surement, event counting, interval measurement, pulse generation, delay timing, pulse width modulation and int
3、errupt generation. Each Timer Counter channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi purpose input/output signals, which can be configured by the user. Each channel drives an internal interrupt signal, which can be programmed to generate processor interrupts via the Advanc
4、ed Interrupt Controller (AIC). The three Timer Counter chan- nels are independent and identical in operation. Each Timer Counter channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0
5、xFFFF and passes to 0x0000, an overflow occurs and the bit COVFS in TCx_SR (Status Register) is set. The current value of the counter is accessible in real-time by reading TCx_CV. A trig- ger can reset the counter. In this case, the counter value passes to 0x0000 on the next valid edge of the select
6、ed clock. AT91 ARM Thumb Microcontroller Application Note 2Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Operating ModesEach Timer Counter channel can operate independently in two different modes: Capture Mode allows measurement on signals Waveform Mode allows wave generation The
7、Timer Counter Operating Mode is programmed with the WAVE bit in the TC Chan- nel Mode Register (TCx_CMR). In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. Trigg
8、erA trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Common TriggersThe following triggers are common to both operating modes: Software Trigger: Each channel has a software trigger, ava
9、ilable by setting SWTRG in TCx_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is impl
10、emented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TCx_CMR. External TriggerThe Timer Counter channel can also be configured to have an external trigger. In Cap- ture Mode, the external trigger signal can be selected between TIOA and TIO
11、B. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trig- ger by setting ENETRG in TCx_CMR. If an external trigger is used, the duration of the pulses must be longer than the system c
12、lock (MCK) period in order to be detected. 3 Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Timer/Counter Block Diagram Figure 1. Timer/Counter Block Diagram Timer/Counter Channel 0 Timer/Counter Channel 1 Timer/Counter Channel 2 SYNC Parallel I/O Controller TC1XC1S TC0XC0S TC2XC2S
13、 INT INT INT TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA0 TIOA1 Advanced Interrupt Controller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Timer Counter Block TIOA TIOB TIOA TIOB T
14、IOA TIOB SYNC SYNC MCK/8 MCK/32 MCK/128 MCK/1024 MCK/2 4Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Clock SourceEach channel can independently select an internal or external clock source for its counter: Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024 External cl
15、ock signals: XC0, XC1 or XC2 The three-bit TCCLKS field of the mode register TCx_CMR determines whether the counter is clocked by one of the five internal clock sources (MCK/x) or one of the three external clock sources (TCLKx). The selected clock can be inverted with the CLKI bit in TCx_CMR (Channe
16、l Mode Reg- ister). This enables counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the
17、 duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock (MCK). Figure 2. Timer/Counter Clock Source The maximal counter duration when an internal clock is used, is determined by the inter-
18、nal clock MCK and the prescaler number: where FTC is in Hz. Table 1. Maximum Counter Duration for Various MCK MCK5 MHz10 MHz20 MHz33 MHz66 MHz MCK/2 26.21ms13.10ms6.55ms3.97ms1.98ms MCK/8104.8ms52.4ms26.22ms14.89ms7.45ms MCK/16419.4ms209.7ms104.86ms63.86ms31.98ms MCK/1281.68s838.8ms420.4ms254.2ms127
19、.1ms MCK/102413.42s6.71s3.36ms2.03s1.02s MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 CLKS 1 Clock Counter 000 001 010 011 100 101 110 111 00 01 10 13 0 1 TCx_MR2:0 Burst TCx_MR5:4 CLKI TCx_MR3 BURSTCLK maximal counter duration (seconds)216FTC= counter resolution1=FTC 5 Interrupt Generation Using
20、 AT91 Timer/Counter 2683BATARM03-10-03 Timer Interrupt Generation Each Timer/Counter channel drives an internal interrupt signal which can be pro- grammed to generate processor interrupts via the AIC (Advanced Interrupt Controller). Each Timer/Counter channel contains a total of 8 interrupts, which
21、can be enabled or disabled from the registers TCx_IER and TCx_IDR. The interrupts are available accord- ing to the operating mode as shown below in Table 2. Application ExampleUse the AT91 Timer/Counter to generate an interrupt and blink one LED every 1s. This application example is based on the AT9
22、1EB40A Evaluation Board but is applicable to all AT91 products. Timer configuration The RC can generate a trigger if bit CPCTRG in the TC Mode Register is set to 1. A trig- ger resets the counter so that RC can control the timer period needed. The RC compare interrupt will be used to generate an int
23、errupt every 1s. The RC compare interrupt is available in both mode, compare and waveform modes so the timer can be configured even in compare mode or in waveform mode. The Master Clock MCK on the AT91EB40A Evaluation Board is 66 MHz. As described previously, the timer period is controlled by the co
24、mpare register RC. The value needed must be determined in the compare register C in order to obtain a timer period of 1s. The minimal prescaler value required to select the timer clock FTC must first be deter- mined. The maximal counter value is 0xFFFF (65535): The value 1007.095 is DIV = 1024. Ther
25、efore the timer clock FTC must be at least MCK/2 MCK/1024 to have a RC compare period of 1s. In an application, the required compare register values must be calculated using the fol- lowing equation: Where t = desired timer compare period (second) FTC = timer clock frequency(Hertz) Compare register
26、RC: Table 2. Operating Mode Interrupts InterruptCapture ModeWaveform Mode Counter Overflow Interrupt COVFSXX Load Overrun Interrupt LOVRSX Compare Register A Interrupt CPASX Compare Register B Interrupt CPBSX Compare Register C Interrupt CPCSXX Load Capture Register A Interrupt LDRASX DIVmint MCK 65
27、535 - -1 66000000 65535 - -1007.095= Compare ValuetFTC)(= RCtFTC() RC1 66000000 1024 - -= 64453=0FBC5 = = 6Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Software Code The following software code example blinks LED8 on the AT91EB40A Evaluation Board every 1s using the Timer/Counter
28、 1 RC compare interrupt and is applicable to the entire AT91 series. This software example is built around two files: irq_timer.s assembly file which defines the assembler timer interrupt assembly handler. timer_interrupt.c C file which includes the main function with the timer configuration and the
29、 C timer interrupt handler. Irq_timer.s ;- ; The software is delivered “AS IS“ without warranty or condition of any kind, either express, implied or statutory. ; This includes without limitation any warranty or condition with respect to merchantability or fitness for any particular purpose, or ; aga
30、inst the ;infringements of intellectual property rights of others. ;- ;- File source : irq_timer.s ;- Object : Assembler timer Interrupt Handler ;- Author : AT91 Application Group ;- ;- ;- Area Definition ;- AREA TIMER_ASM_HANDLER, CODE, READONLY AIC_BASE EQU 0xFFFFF000 AIC_IVR EQU 0x100 AIC_EOICR E
31、QU 0x130 ;- ARM Core Mode and Status Bits ARM_MODE_IRQ EQU 0x12 ARM_MODE_SYS EQU 0x1F I_BIT EQU 0x80 MACRO IRQ_ENTRY $reg ;- Adjust and save LR_irq in IRQ stack sub r14, r14, #4 stmfd sp!, r14 ;- Write in the IVR to support Protect Mode ;- No effect in Normal Mode ;- De-assert the NIRQ and clear the
32、 source in Protect Mode ldr r14, =AIC_BASE 7 Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 str r14, r14, #AIC_IVR ;- Save SPSR and r0 in IRQ stack mrs r14, SPSR stmfd sp!, r0, r14 ;- Enable Interrupt and Switch in SYS Mode mrs r0, CPSR bic r0, r0, #I_BIT orr r0, r0, #ARM_MODE_SYS
33、msr CPSR_c, r0 ;- Save scratch/used registers and LR in User Stack IF “$reg“ = “ stmfd sp!, r1-r3, r12, r14 ELSE stmfd sp!, r1-r3, $reg, r12, r14 ENDIF MEND MACRO IRQ_EXIT $reg ;- Restore scratch/used registers and LR from User Stack IF “$reg“ = “ ldmia sp!, r1-r3, r12, r14 ELSE ldmia sp!, r1-r3, $r
34、eg, r12, r14 ENDIF ;- Disable Interrupt and switch back in IRQ mode mrs r0, CPSR bic r0, r0, #ARM_MODE_SYS orr r0, r0, #I_BIT:OR:ARM_MODE_IRQ msr CPSR_c, r0 ;- Mark the End of Interrupt on the AIC ldr r0, =AIC_BASE str r0, r0, #AIC_EOICR ;- Restore SPSR_irq and r0 from IRQ stack ldmia sp!, r0, r14 m
35、sr SPSR_cxsf, r14 ;- Restore adjusted LR_irq from IRQ stack directly in the PC ldmia sp!, pc MEND 8Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 ;- ;- Function : timer1_asm_irq_handler ;- Treatments : Timer 1 interrupt handler. ;- Called Functions : timer1_c_irq_handler ;- Called
36、Macros : IRQ_ENTRY, IRQ_EXIT ;- EXPORT timer1_asm_irq_handler IMPORT timer1_c_irq_handler timer1_asm_irq_handler ;- Manage Exception Entry IRQ_ENTRY ;- Call the timer Interrupt C handler ldr r1, =timer1_c_irq_handler mov r14, pc bx r1 ;- Manage Exception Exit IRQ_EXIT END Timer_interrupt.c /*- /* Fi
37、le Name: Timer_interrupt.c /* Object : AT91EB40A - Timer Counter - Interrupt /* Author: AT91 Application Group /*- #defineTC1_CCR(volatile unsigned int *) 0xFFFE0040) #define TC1_CMR(volatile unsigned int *) 0xFFFE0044) #define TC1_RC(volatile unsigned int *) 0xFFFE005C) #define TC1_SR(volatile unsi
38、gned int *) 0xFFFE0060) #define TC1_IER(volatile unsigned int *) 0xFFFE0064) #define TC1_IDR(volatile unsigned int *) 0xFFFE0068) #define PIO_PER(volatile unsigned int *) 0xFFFF0000) #define PIO_OER(volatile unsigned int *) 0xFFFF0010) #define PIO_SODR(volatile unsigned int *) 0xFFFF0030) #define PI
39、O_CODR(volatile unsigned int *) 0xFFFF0034) #define PIO_PDSR(volatile unsigned int *) 0xFFFF003C) #define AIC_SMR5(volatile unsigned int *) 0xFFFFF014) #define AIC_SVR5(volatile unsigned int *) 0xFFFFF094) #define AIC_IECR(volatile unsigned int *) 0xFFFFF120) #define AIC_IDCR(volatile unsigned int *
40、) 0xFFFFF124) #define AIC_ICCR(volatile unsigned int *) 0xFFFFF128) #define TC1_ID5 /* Timer Channel 1 interrupt */ 9 Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 /* TC_CMR: Timer Counter Channel Mode Register Bits Definition #define TC_CLKS_MCK1024 0x4 #define TC_CPCTRG 0x4000 /
41、* TC_CCR: Timer Counter Control Register Bits Definition #define TC_CLKEN 0x1 #define TC_CLKDIS 0x2 #define TC_SWTRG 0x4 /* TC_SR: Timer Counter Status Register Bits Definition #define TC_CPCS 0x10 /* RC Compare Status */ /* AIC_SMR: Interrupt Source Mode Registers #define AIC_SRCTYPE_INT_LEVEL_SENS
42、ITIVE 0x00 /* Level Sensitive */ /* Leds Definition #define LED1 (116) #define LED8 (16) extern void timer1_asm_irq_handler(void); /*- /* Function Name : timer1_c_irq_handler /* Object : Timer 1 interrupt Handler /*- void timer1_c_irq_handler (void) /* Begin unsigned int dummy ; dummy = *TC1_SR; /*
43、Read TC1 Status Register to clear it */ if ( (*PIO_PDSR else *PIO_SODR = LED8 ; /* End void delay (void) unsigned int i; for (i=0; i1000000 ; i+); 10Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 /*- /* Function Name : main /* Object : AT91 - Timer Counter- PWM generation /* Input
44、Parameters : none /* Output Parameters : none /* Functions called : none /*- int main ( void ) /* Begin unsigned int dummy ; *PIO_PER = LED8 | LED1 ; /* Enable the PIO/LED8 pin */ *PIO_OER = LED8 | LED1; /* Enable the PIO/LED8 pin as Output */ *PIO_CODR = LED8 | LED1 ; /* Set LED8 */ / Timer1 Init *TC1_CCR = TC_CLKDIS ; /* Disable the Clock Counter */ *TC1_IDR = 0xFFFFFFFF ; dummy = *TC1_SR ; *TC1_C