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1、Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives. IT8209R Extended PCI Arbiter and Clock Buffer Preliminary Specification V0.3.1 ITE TECH. INC. Copyright ? 2005 ITE Tech. Inc. This is Preliminary document release. All
2、specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITEs Standard Terms and Conditions, a
3、 copy of which is included in the back of this document. ITE, IT8209R is a trademark of ITE Tech. Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from:
4、ITE Tech. Inc. Phone: (02) 2912-6889 Marketing Department Fax: (02) 2910-2551, 2910-2552 8F, No. 233-1, Bao Chiao RD., Hsin Tien, Taipei County 231, Taiwan, R.O.C. If you have any marketing or sales questions, please contact: P.Y. Chang , at ITE Taiwan: E-mail: .tw, Tel: 886-2-29126889 X6052, Fax: 8
5、86-2-29102551 To find out more about ITE, visit our World Wide Web at: http:/.tw Or e-mail .tw for more product information/services .tw IT8209R V0.3.1 1 Revision History Revision History Section Revision Page No. 9 ? Added the following content in the ordering information: “ITE also provides lead-f
6、ree component. Please mark “ -L “ at the end of the Part No. when the parts ordered are lead-free.” 17 .tw IT8209R V0.3.1 i Contents Contents 1. Features.1 2. General Description3 3. Block Diagram5 4. Pin Configuration7 5. IT8209R Pin Descriptions.9 6. DC Characteristics (VCC, AVCC = 3.3V 0.3V. Ta=0
7、 C to 70 C)11 7. AC Characteristics13 8. Package Information15 9. Ordering Information17 Figures Figure 2-1. Arbitration Scheme of IT8209R3 Figure 3-1. Extended PCI Arbiter Scheme5 Figure 3-2. Clock Buffer Scheme5 Figure 7-1. PCI Request Delay Timing.13 Figure 7-2. PCI Grant Delay Timing13 Figure 7-
8、3. PCI Grant Separation Timing13 Figure 7-4. PCI Clock Acquisition Timing14 Tables Table 4-1. Pins Listed in Numeric Order.7 Table 5-1. Pin Descriptions of Extended PCI Arbiter9 Table 5-2. Pin Descriptions of Clock Buffer9 Table 5-3. Pin Descriptions of Power/Ground Signals9 Table 7-1. PCI Request D
9、elay Timing Table.13 Table 7-2. PCI Grant Delay Timing Table.13 Table 7-3. PCI Grant SeparatioinTiming Table.13 Table 7-4. PCI Clock Acquisition Timing Table.14 .tw IT8209R V0.3.1 ITPM-PN-200517 Specifications subject to change without notice By Jason Tsai, 5/27/2005 1 Features 1. Features Extended
10、PCI Arbiter - Utilizes 1 set of SYSGNT# and SYSREQ# to support 3 PCI Masters Input PCI Clock - Supports input clock frequency from 25MHz to 66MHz Clock Buffer - Provides 4 zero delay clock sources - Supports output clock frequency from 25MHz to 66MHz 28-pin SSOP .tw IT8209R V0.3.1 2 This page is int
11、entionally left blank. .tw IT8209R V0.3.1 3 General Description 2. General Description The IT8209R incorporates an extended PCI arbiter and a clock buffer. The extended PCI arbiter utilizes one set of SYSGNT# and SYSREQ# to support 3 PCI Masters, so that two more PCI Masters can be supported for the
12、 system. PCISTOP# input signal is useful to facilitate the fairness arbitration. The algorithm of this arbiter uses a rotation arbitration priority that is illustrated in Figure 2-1. The clock buffer provides 4 zero delay and low jitter clock sources. PCICLKI is the clock input of the clock buffer,
13、and PCICLKOUT is the clock output fed back internally to the input of the built-in PLL to reduce the clock skew. If zero clock skew is required, PCICLKOUT and PCICLK1 to PCICLK4 must be equally loaded. When PCICLKI input becomes inactive, the IT8209R will enter power down mode. In power down mode, a
14、ll clock outputs are low and other control outputs are deasserted. The IT8209R is available in 28-pin SSOP package. Figure 2-1. Arbitration Scheme of IT8209R Extended Device 1 Extended Device 3 Extended Device 2 PCI Device n PCI Device x PCI Device n-1 PCI Device 1 PCI Device 2 Central PCI Arbiter (
15、Chipset) Extended PCI Arbiter (IT8209R) .tw IT8209R V0.3.1 4 This page is intentionally left blank. .tw IT8209R V0.3.1 5 Block Diagram 3. Block Diagram Figure 3-1. Extended PCI Arbiter Scheme Figure 3-2. Clock Buffer Scheme IT8209R PCICLKI Clock Generator PCI Device 1 PCICLK1 PCICLK2 PCICLK3 PCICLK4
16、 PCICLKOUT PCI Device 2 PCI Device 3 PCI Device 4 Load P C I B u s IT8209R SYSREQ# SYSGNT# PCIREQ1# PCIGNT1# PCIREQ2# PCIGNT2# PCIREQ3# PCIGNT3# PCI Master 1 PCI Master 2 PCI Master 3 .tw IT8209R V0.3.1 6 This page is intentionally left blank. .tw IT8209R V0.3.1 7 Pin Configuration 4. Pin Configurat
17、ion 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 18 17 16 15 24 23 22 21 20 28 27 26 25 IT8209R PCISTOP# SYSREQ# SYSGNT# PCIREQ1# VSS PCIGNT1# PCIREQ2# VCC PCIGNT2# PCIREQ3# PCIGNT3# NC NC AVCC PCICLKI PCIRST# AVSS VSS PCICLKOUT PCICLK1 VCC PCICLK2 PCICLK3 PCICLK4 VSS NC NC PCIFRAME# Pin Signal Pin Signal 1
18、PCIFRAME# 15 NC 2 PCISTOP# 16 NC 3 SYSREQ# 17 VSS 4 SYSGNT# 18 PCICLK4 5 PCIREQ1# 19 PCICLK3 6 VSS 20 PCICLK2 7 PCIGNT1# 21 VCC 8 PCIREQ2# 22 PCICLK1 9 VCC 23 PCICLKOUT 10 PCIGNT2# 24 VSS 11 PCIREQ3# 25 AVSS 12 PCIGNT3# 26 PCIRST# 13 NC 27 PCICLKI 14 NC 28 AVCC Table 4-1. Pins Listed in Numeric Orde
19、r .tw IT8209R V0.3.1 8 This page is intentionally left blank. .tw IT8209R V0.3.1 9 IT8209R Pin Descriptions 5. IT8209R Pin Descriptions Table 5-1. Pin Descriptions of Extended PCI Arbiter Signal Pin(s) No. Attribute Description Extended PCI Arbiter Signals (3.3V CMOS I/F, 5V tolerant) PCIFRAME# 1 PI
20、U PCI Bus FRAME# Signal The pin can be connected to PCI Bus FRAME# signal or not connected to any signals. PCISTOP# 2 PIU PCI Bus STOP# Signal SYSREQ# 3 O12 PCI Bus Request SYSGNT# 4 PIU PCI Bus Grant PCIREQ1# 5 PIU Request Signal from Extended PCI Master 1 PCIGNT1# 7 O12 Grant Signal to Extended PC
21、I Master 1 PCIREQ2# 8 PIU Request Signal from Extended PCI Master 2 PCIGNT2# 10 O12 Grant Signal to Extended PCI Master 2 PCIREQ3# 11 PIU Request Signal from Extended PCI Master 3 PCIGNT3# 12 O12 Grant Signal to Extended PCI Master 3 PCIRST# 26 IK PCI Bus RST# Signal Table 5-2. Pin Descriptions of C
22、lock Buffer Signal Pin(s) No. Attribute Description Clock Buffer Signals (3.3V CMOS I/F) PCICLK4 18 O12 PCICLK Output 4 PCICLK3 19 O12 PCICLK Output 3 PCICLK2 20 O12 PCICLK Output 2 PCICLK1 22 O12 PCICLK Output 1 PCICLKOUT 23 O12 PCICLK Output (for internal feedback) PCICLKI 27 I PCICLK Input Table
23、5-3. Pin Descriptions of Power/Ground Signals Signal Pin(s) No. Attribute Description Power Ground Signals VSS 6, 17, 24 I Ground VCC 9, 21 I Power Supply of 3.3V AVSS 25 I Analog Ground for analog PLL AVCC 28 I Analog VCC for analog PLL Notes: IO cell types are described as below: I: Input PAD. IK:
24、 Schmitt Trigger Input PAD. PIU: PCI Bus Specified Input PAD (integrated a 75K ohms pull-up resistor). O12: 12mA Output PAD. .tw IT8209R V0.3.1 10 This page is intentionally left blank. .tw IT8209R V0.3.1 11 DC Characteristics 6. DC Characteristics (VCC, AVCC = 3.3V 0.3V. Ta=0 C to 70 C) Absolute Ma
25、ximum Ratings* Applied Voltage of VCC, AVCC -0.3V to +4.6V Input Voltage of 3.3V Interface-0.3V to VCC+0.3V Input Voltage of 5V tolerant Interface -0.3V to 5.25V Tcase.0 C to +70 C Storage Temperature.-40 C to +125 C DC Electrical Characteristics (Ta = 0 C to 70 C) Symbol Parameter Min. Typ. Max. Co
26、nditions VIL Input Low Voltage - 0.3V VCC x 0.3VCC=3.0 3.6V VIHInput High Voltage VCC x 0.7VCC=3.0 3.6V VOLOutput Low Voltage 0.5 IOL= -12mA VOHOutput High Voltage 2.4 IOH= 12mA IILInput Low Current -1 A 1 A VIL= VSS no pull-up or pull-down IIH Input High Current -1 A 1 A VIH= VCC no pull-up or pull
27、-down IOZ Tri-state Leakage Current -10 A 10 A Cin Input Capacitance 3pF Cout Output Capacitance 3pF Cbld Bi-directional Buffer 3pF RIInput Pull-Up Resistance 40K?75K?170K? VIL =0V *Comments Stresses above those listed under “Absolute Maximum Ratings“ may cause permanent damage to this device. These
28、 are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability. .tw IT8209R V0
29、.3.1 12 This page is intentionally left blank. .tw IT8209R V0.3.1 13 AC Characteristics 7. AC Characteristics Figure 7-1. PCI Request Delay Timing Table 7-1. PCI Request Delay Timing Table Symbol Parameter Min. Typ.Max. Unit t1PCIREQn# (n=1, 2, 3) to SYSREQ# asserted 0 - 7 ns Figure 7-2. PCI Grant D
30、elay Timing Table 7-2. PCI Grant Delay Timing Table Symbol Parameter Min. Typ.Max. Unit t2SYSGNT# to PCIGNTn# (n=1, 2, 3) asserted 0 - 8.5 ns Figure 7-3. PCI Grant Separation Timing Table 7-3. PCI Grant Separation Timing Table Symbol Parameter Min. Typ.Max. Unit t3 PCIGNTm# (m=1, 2, 3) deasserted to
31、 PCIGNTn# (n=1, 2, 3) asserted (n != m) 1 - - Clock Period PCIREQn# SYSREQ# t1 SYSGNT# PCIGNTn# t2 PCIGNTm# PCIGNTn# t3 .tw IT8209R V0.3.1 14 IT8209R Figure 7-4. PCI Clock Acquisition Timing Table 7-4. PCI Clock Acquisition Timing Table Symbol Parameter Min. Typ.Max. Unit t4PCICLKI stable to PCICLKn
32、 (n=1, 2, 3, 4, out) stable- - 60 us PCICLKI PCICLKn t4 .tw IT8209R V0.3.1 15 Package Information 8. Package Information SSOP28L Outline Dimensions unit: inches/mm e D y Dimension in inchesDimension in mm Symbol MinNomMaxMinNomMax A 0.0530.0640.0691.351.631.75 A1 0.0040.0060.0100.100.1520.25 A2 0.05
33、9 1.50 b 0.0080.0100.0120.2030.2540.305 C 0.0070.0100.1780.250 D 0.3860.3900.3949.809.9110.00 E 0.1500.1540.1573.803.914.00 e 0.025BSC 0.635BSC HE 0.2280.2360.2445.805.996.20 L 0.0160.0250.0500.400.6351.27 L1 0.041REF. 1.04REF. S 0.033REF. 0.838REF. y 0.004 0.10 0808 Note: 1. Controlling dimensionin
34、ch 2. DimensionDandEdo not include mold protrusion. DandEare maximum plastic body size dimension including mold mismatch. 3. Dimensionbdose not include dambar protrusion. Damber cannot be located on the lower radius of the foot. 4. Reference DocumentJEDEC SPEC MO-137. DI-SSOP28(150mil Body)v2 .tw IT8209R V0.3.1 16 This page is intentionally left blank. .tw IT8209R V0.3.1 17 Ordering Information 9. Ordering Information Part No. Package IT8209R 28 SSOP ITE also provides lead-free component. Please mark “ -L “ at the end of the Part No. when the parts ordered are lead-free.