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1、3D IC technology 惰 公 昂 阔 辐 辣 樱 化 剧 墒 粹 国 答 卯 址 插 遏 傀 茬 尝 螟 迢 超 赛 贾 玫 尤 屯 偶 鞍 瞎 尔 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y What is a 3D IC? “Stacked” 2D (Conventional) ICsCould be Heterogeneous 亦 啊 山 弛 售 詹 捉 引 感 雅 宛 宴 调 妈 枉 狗 捂 逼 蹿 舰 买 坪 谜 玫 愧 占 黎 福 迅 忆 蚜 益 3 D I C t e c h n o l o g y
2、3 D I C t e c h n o l o g y Motivation nInterconnect structures increasingly consume more of the power and delay budgets in modern design nPlausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design nSmaller wire cross-sections, smaller wire pitch and
3、 longer lines to traverse larger chips increase RC delay. RC delay is increasingly becoming the dominant factor nAt 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay. n 130 nm technology node, substantial interconnect delays will result. 裤 栏 和 亿 额 阵 蛔 贺 练 藉 佐 小 泞
4、 乞 挖 冬 绊 议 刀 怔 独 促 牙 凸 缀 毁 爱 翁 忧 谈 轧 艺 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 3D Fabrication Technologies nMany options available for realization of 3D circuits nChoice of Fabrication depends on requirements of Circuit System Beam Recrystallization Processed Wafer Bonding Silicon Ep
5、itaxial Growth Solid Phase Crystallization Deposit polysillicon and fabricate TFTs -not practial for 3D circuits due to high temp of melting polysillicon -Suffers from Low carrier mobility -However high perfomance TFTs have been fabricated using low temp processing which can be used to implement 3D
6、circuits Bond two fully processed wafers together. -Similar Electrical Properties on all devices -Independent of temp. since all chips are fabricated then bonded -Good for applications where chips do independent processing -However Lack of Precision(alignemnt) restricts interchip communication to gl
7、obal metal lines. Epitaxially grow a single cystal Si -High temperatures cause siginificant cause significant degradation in quality of devices on lower layers -Process not yet manufacturable Low Temp alternative to SE. -Offers Flexibilty of creating multiple layers -Compatible with current processi
8、ng environments -Useful for Stacked SRAM and EEPROM cells 熟 彝 绦 链 寄 妻 写 洞 痪 犹 街 打 睬 渝 尼 卑 抡 证 鹿 磐 学 架 篇 舍 寡 重 雌 龚 恕 兰 蠕 腾 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Performance Characteristics nTiming nEnergy nWith shorter interconnects in 3D ICs, both switching energy and cycle time ar
9、e expected to be reduced 角 饭 涵 亭 吻 筛 何 畸 尾 摸 趟 钵 津 舅 迅 耀 踞 话 阅 联 硒 厌 吸 谐 趟 派 广 芋 将 张 辖 沸 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Timing nIn current technologies, timing is interconnect driven. nReducing interconnect length in designs can dramatically reduce RC delays and increase chi
10、p performance nThe graph below shows the results of a reduction in wire length due to 3D routing nDiscussed more in detail later in the slides 蒲 幼 翻 迸 闻 闺 让 宦 帛 团 倘 舆 腥 徐 隶 继 涂 倒 扯 白 拉 署 锚 狐 凶 桔 旗 袭 啥 翔 挤 珍 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Energy performance nWire length reduc
11、tion has an impact on the cycle time and the energy dissipation nEnergy dissipation decreases with the number of layers used in the design nFollowing graphs are based on the 3D tool described later in the presentation 查 奔 工 侯 蛋 渍 亭 枫 讹 最 题 御 毗 闰 赂 罕 氟 香 丙 碗 夹 闷 谐 抠 报 俏 酣 懊 耀 胃 榔 觉 3 D I C t e c h n
12、o l o g y 3 D I C t e c h n o l o g y Energy performance graphs 造 侩 和 蚀 床 频 赶 戳 牵 涯 设 垣 智 样 肝 亏 地 芒 腺 秸 琅 咖 烹 睹 着 逝 掐 寒 蛹 扬 射 摆 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Design tools for 3D-IC design nDemand for EDA tools As the technology matures, designers will want to exploit this d
13、esign area nCurrent tool-chains Mostly academic nWe will discuss a tool from MIT 熊 驰 蔼 毗 屎 止 匡 钳 和 针 瑶 经 搅 葱 涡 糟 块 乎 桃 爵 肄 碳 炳 桅 提 前 蔚 享 机 晦 驻 拱 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 3D Standard Cell tool Design n3D Cell Placement Placement by min-cut partitioning n3D Global Routin
14、g Inter-wafer vias nCircuit layout management MAGIC 礁 于 漆 洛 处 詹 沪 沉 千 楔 砧 瞻 兹 辱 逛 灶 涝 针 疮 芒 柜 层 毁 诺 寅 馋 汞 关 笺 痊 测 门 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 3D Standard Cell Placement nNatural to think of a 3D integrated circuit as being partitioned into device layers or planes nMin c
15、ut part-itioning along the 3rd dimension is same as minimizing vias 但 五 唇 股 请 学 硕 悠 云 约 伞 呛 悸 们 怕 沼 距 瓢 鸯 凑 梯 绞 及 萤 卸 高 铣 铜 畔 犁 杨 拥 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Total wire length vs. Vias nCan trade off increased total wire length for fewer inter-plane vias by varying the
16、point at which the design is partitioned into planes Plane assignment performed prior to detailed placement nYields smaller number of vias, but greater overall wire length 丫 挞 输 偏 涣 啤 十 之 屡 墙 痘 捅 帐 闪 柯 王 瞳 渠 麦 联 施 渴 如 屡 暮 皇 关 仓 埔 车 泊 网 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Total wi
17、re length vs. Vias (Cont) Plane assignment not made until detailed placement stage nYields smaller total wire length but greater number of vias 揉 赫 劈 素 治 搔 越 撇 追 蝎 臣 十 保 砾 系 彼 臼 喧 悯 言 氢 苗 症 屎 嘱 诡 扣 依 矮 难 奇 湘 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Intro to Global Routing nOverview Gl
18、obal Routing involves generating a “loose” route for each net. nAssigns a list of routing regions to a net without actually specifying the geometrical layout of the wires. Followed by detailed routing nFinds the actual geometrical shape of the net within the assigned routing regions. Usually either
19、sequential or hierarchical algorithms 敛 怂 泌 栓 篮 拍 绪 罚 警 罪 壮 叉 窍 漳 靠 嘴 枣 奸 即 下 腐 阔 惩 末 韵 镀 西 畏 代 引 士 泰 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Illustration of routing areas x z y x z y Detailed routing of net when routing areas are known 亨 猫 热 坍 聚 暑 销 色 竹 卖 顿 滁 支 拭 巾 唆 驴 讶 笆 孟 息 碑 葫 怜
20、 肩 绊 翼 脏 认 丛 瘟 显 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Hierarchical Global Routing nTool uses a hierarchical global routing algorithm Based on Integer programming and Steiner trees Integer programming approach still too slow for size of problem and complexity (NP-hard) Hierarchical
21、 routing methods break down the integer program into pieces small enough to be solved exactly 臻 就 炊 匆 葵 串 气 踏 认 藏 象 避 腊 行 进 躺 肝 肝 汽 报 晌 刘 剃 催 惜 蘸 淮 违 玩 产 磊 匪 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 2D Global Routing nA 2D Hierarchical global router works by recursively bisecting the
22、routing substrate. Wires within a Region are fully contained or terminate at a pin on the region boundry. nAt each partitioning step the pins on the side of the routing region is allocated to one of the two subregions. nWires Connect cells on both sides of the partition line. These are cut by the pa
23、rtition and for each a pin is inserted into the side of the partition nOnce complete, the results can be fed to a detailed router or switch box router (A switchbox is a rectangular area bounded on all sides by blocks) 灌 炸 潭 罗 慢 站 镰 折 伯 袒 八 怠 捅 皖 萤 剩 箭 剩 尧 衷 呛 芯 菏 融 兴 雍 吁 岭 坯 居 幂 蚊 3 D I C t e c h n
24、o l o g y 3 D I C t e c h n o l o g y Illustration of Bisection 槛 疤 闽 违 繁 隋 娠 位 骗 八 概 灯 膨 鸣 嗜 产 氖 卓 廉 吊 损 充 镐 点 锭 至 冉 而 腺 在 李 胯 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Extending to 3D nRouting in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers. Wi
25、res can enter from any of the sides of the routing region in addition to its top and bottom n3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias nBasis idea is: You connect a inter-waver via to the port you are trying to connect to, and route th
26、e wire to that via on the 2D plane. All we need now is enough area in the 2D routing space to route to the appropriate via 村 复 亚 焉 艾 温 蝗 奉 完 呜 落 酱 沪 骑 敢 灭 驴 认 鸣 溢 赣 较 澎 陕 廓 榆 碴 寄 竣 贞 尧 竿 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 3D Routing Results Percentage Of 2D Total wire Length Min
27、imizing for Wire Length: 2 Layers 28% 5 Layers 51 % Minimizing for via count: 2 Layers 7% 5 Layers 17% 慎 狱 嗅 疥 裕 诀 筐 释 来 阔 绅 厢 岸 赐 皑 源 津 掩 赃 佩 为 蹋 琅 坝 教 据 仟 央 创 肿 丘 晤 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y 3D-MAGIC nMAGIC is an open source layout editor developed at UC Berkeley n3D-
28、MAGIC is an extension to MAGIC by providing support for Multi-layer IC design nWhats different New Command :bond Bonds existing 2D ICs and places inter-layer Vias in the design file Once Two layers are bonded they are treated as one entity 窗 切 抓 畦 梳 皆 磋 痕 怪 翟 透 榷 饱 勉 帖 调 剪 愿 邢 偶 载 昨 位 事 绽 劲 痰 打 怕 蛮
29、起 测 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Concerns in 3D circuit nThermal Issues in 3D-circuits nEMI nReliability Issues 湃 苟 遥 绣 帮 森 恒 描 凯 文 痊 釜 悉 淌 辟 艇 偶 纠 彩 啮 嫩 尊 屈 瑞 鱼 粕 册 城 脯 另 寄 倘 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Thermal Issues in 3D Circuits nThermal Ef
30、fects dramatically impact interconnect and device reliability in 2D circuits nDue to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density nAnalysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and des
31、ign options. 匙 躯 江 跳 神 引 稻 念 榴 瓶 苯 嘴 耕 带 搬 黔 宰 晓 据 溺 败 写 些 货 熔 刻 心 侩 晴 兔 瓣 赠 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Heat Flow in 2D Heat generated arises due to switching In 2D circuits we have only one layer of Si to consider. 哄 苍 囊 岭 巾 计 碾 杯 说 脚 棘 荚 服 儡 赢 偷 舔 炸 卞 咖 敦 逮 猖 浑 疼 穗 劣 僧
32、 姥 疽 错 哟 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Heat Flow in 3D With multi-layer circuits , the upper layers will also generate a significant fraction of the heat. Heat increases linearly with level increase 唱 溯 寅 殆 压 镐 翱 貌 腾 曰 六 伪 闺 市 攫 致 琐 扎 嫁 甄 溺 粘 荐 旦 辈 研 盂 萎 叫 困 毁 恰 3 D I C t e
33、 c h n o l o g y 3 D I C t e c h n o l o g y Heat Dissipation nAll active layers will be insulated from each other by layers of dielectrics nWith much lower thermal conductivity than Si nTherefore heat dissipation in 3D circuits can accelerate many failure mechanisms. 简 暴 烙 谣 拾 毋 白 依 勺 帽 八 搂 堕 伸 贵 瞒
34、 儿 铀 谣 饰 奸 彦 谣 电 失 棱 辞 醉 利 辙 鸳 须 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Heat Dissipation in Wafer Bonding versus Epitaxial Growth nWafer Bonding(b) 2X Area for heat dissipation nEpitaxial Growth(a) 损 纽 似 沦 轧 曳 儒 斧 审 侗 麻 需 证 馋 储 欠 芝 薄 抹 哺 软 犀 沛 贯 晤 堡 攒 鉴 标 崔 皆 悯 3 D I C t e c h n o l
35、 o g y 3 D I C t e c h n o l o g y Heat Dissipation in Wafer Bonding versus Epitaxial Growth nDesign 1 Equal Chip Area nDesign 2 Equal metal wire pitch 累 赫 舜 窃 絮 戚 纵 傅 厦 都 籽 嚼 太 皱 着 鸳 襟 眺 箩 籽 雇 涪 赤 彰 企 引 坎 则 基 炎 跪 破 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y High epitaxial temperature T
36、emperatures actually higher for Epitaxial second layers Since the temperature of the second active layer T2 will Be higher than T1 since T1 is closer to the substrate and T2 is stuck between insulators 滋 吉 纸 潍 沮 残 冀 亥 顿 藩 器 石 逐 纫 讶 济 皂 必 撅 栏 寸 汝 辞 琵 穗 垒 颂 咬 携 惮 硕 胡 3 D I C t e c h n o l o g y 3 D I
37、C t e c h n o l o g y EMI in 3D ICs nInterconnect Coupling Capacitance and cross talk Coupling between the top layer metal of the first active layer and the device on the second active layer devices is expected 尖 切 秽 士 拂 阻 剪 闭 卉 靴 班 耸 助 蔚 袒 启 棉 萌 肖 獭 穿 凌 氓 西 底 靴 康 哲 隘 趴 运 撒 3 D I C t e c h n o l o g
38、 y 3 D I C t e c h n o l o g y EMI nInterconnect Inductance Effects Shorter wire lengths help reduce the inductance Presence of second substrate close to global wires might help lower inductance by providing shorter return paths 惊 竭 磊 胃 震 征 各 主 葛 超 卵 墓 甜 哭 媚 尺 掠 滥 泰 难 凶 从 唬 阔 汾 郸 拘 吗 千 终 釜 握 3 D I C
39、 t e c h n o l o g y 3 D I C t e c h n o l o g y Reliability Issues? nElectro thermal and Thermo-mechanical effects between various active layers can influence electro- migration and chip performance nDie yield issues may arise due to mismatches between die yields of different layers, which affect n
40、et yield of 3D chips. 喂 箩 淖 斧 街 惑 葵 粥 良 麦 氦 见 舱 陷 碟 煎 兄 希 其 勤 愧 屉 肛 萝 澈 戴 沈 间 窒 塞 现 酌 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Implications on Circuit Design and Architecture nBuffer Insertion nLayout of Critical Paths nMicroprocessor Design nMixed Signal ICs nPhysical design and Synt
41、hesis 鹤 差 幅 村 笋 梅 夹 挝 朝 篷 雅 锄 害 钵 窜 叙 崩 袍 跑 怜 杜 戈 咖 浪 铜 逸 艾 企 毛 骗 鹰 骚 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y nBuffer Insertion Use of buffers in 3D circuits to break up long interconnects At top layers inverter sizes 450 times min inverter size for the relevant technology These top
42、layer buffers require large routing area and can reach up to 10,000 for high performance designs in 100nm technology With 3D technology repeaters can be placed on the second layer and reduce area for the first layer. Buffer Insertion 避 更 汁 痔 唐 耸 督 瞥 授 近 伟 婿 限 等 簿 韩 委 丸 疑 觅 镀 折 莲 滩 泼 煤 剔 惑 屑 房 仔 颗 3
43、D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Layout of Critical Paths and Microprocessor Design nOnce again interconnect delay dominates in 2D design. nLogic blocks on the critical path need to communicate with each other but due to placement and desig constraints are placed far away from e
44、ach other. nWith a second layer of Si these devices can be placed on different layes of Si and thus closer to each other using(VILICs) nIn Microprocessor design most critical paths involve on chip caches on the critical path. nComputational modules which access the cache are distributed all over the
45、 chip while the cache is in the corner. nCache can be placed on a second layer and connected to these modules using (VILICs) 醋 恕 齐 降 靛 夏 赋 眠 怔 意 瑶 阔 因 种 汞 容 滓 灭 龄 辱 惫 谍 吟 授 幸 郡 殊 怒 吨 碘 谚 做 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Mixed Signal ICs and Physical Design nDigital signals o
46、n chip can couple and interfere with RF signals nWith multiple layers RF portions of the system can be separated from their digital counterparts. nPhysical Design needs to consider the multiple layers of Silicon available. nPlacement and routing algorithms need to be modified 疮 窟 塑 沟 将 首 讶 郭 咐 毋 沃 谆
47、 懊 笋 趋 院 翰 意 毗 圆 槐 陶 丙 昏 汲 孟 盎 氛 珐 煽 置 汕 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y Conclusion n3D IC design is a relief to interconnect driven IC design. nStill many manufacturing and technological difficulties nNeeds strong EDA applications for automated design 放 歼 圃 赖 林 镭 胰 害 橱 排 寥 湖 准 乃 阶 锅 偶 据 售 搁 瞎 彩 淤 髓 沿 工 迅 卒 悼 矢 丙 羽 3 D I C t e c h n o l o g y 3 D I C t e c h n o l o g y