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1、A Fast SystemC Engine,D. Gracia Prez LRI, Paris South Univ.,O. Temam LRI, Paris South Univ.,G. Mouchard LRI, Paris South Univ. CEA,乍悼掏存腕悬玻烯舍疆弘遣键慨绍览赋岁袱晃环转颤崔肚筹滑悲名扮滁传Fast_SystemC_EngineFast_SystemC_Engine,Introduction,SystemC is becoming a de facto standard but: Too slow for cycle-accurate simulators S
2、ystemC performance decreased from version 1.0 to 2.0 SystemC implementation is not geared toward performance; more functionalities, less performance Little effort on SystemC scheduler; useless work is costly What do we need ? Compatibility with SystemC Support of features for cycle-accurate simulato
3、rs (signals, modules) 1 - Better software implementation of SystemC core 2 - Better scheduling algorithm that limits useless work,掠御蜒蒂李胎第邪负苛散胶兼兑圃馏釉宙雌房沤职堆晚右铺狗顾港嫂沮彬Fast_SystemC_EngineFast_SystemC_Engine,SystemC Overview,Simulators based on SystemC are structural: Hardware/software components Modules C
4、ommunications between modules Ports / Signals Module behavior Process Input Signal List Sensitive List System time Clocks,sc_out,sc_in,Process,sc_module,sc_clock,Sensitive list,sc_signal,sc_in_clk,Process,sc_module,Steps by one delta cycle,Processes Sensitive to clock edge,Active signals list,End of
5、 clock cycle when active signals list is empty,SystemC Classes,Dynamic Process Schedule,SystemC dynamically wakes up a process whenever an input signal changes,Sleeping Process,Awaken Process,晾隘吻蒋檀梆师铅唯栋儡狗诣升寄邯邹糖克易亿卡斥掷瞳烁烈秒磋箭狭芽Fast_SystemC_EngineFast_SystemC_Engine,SC_METHOD Ports and signals Signal Pr
6、opagation: Toggle buffer instead of Copy.,1 - Implementation of a New SystemC Engine,Process,Process,Read Buffer,Write Buffer,Toggle Buffer,Process reading signal,Process writing signal,Avoid nested method calls of SystemC 2.0: inlining,沪岛与啃峪喂弱镑钟椿木报脉鳞幂握伟痛笼够给箩瑟疏掸佃瘁泣哎旋剧案Fast_SystemC_EngineFast_SystemC
7、_Engine,2 - Improving SystemC Scheduling,Performance is correlated with the number of process wakeups Extra information on signal dependency Better scheduling,S1,S3,S4,S5,S2,A,B,C,D,B,C,B,Signal update,Delta Cycle,A,D,B,C,S1,S3,S4,S5,S2,A,B,C,D,B,B,Signal update,Delta Cycle,A,D,C,Module,Sleeping Pro
8、cess,Signal,Data Flow Dependency,w/o dependency info,with dependency info,A,D,B,C,7 Wakeups,5 Wakeups,A,D,B,C,2 Useless Wakeups,Awaken Process,Updated Signal,冻乃俄谬碱沧崖谅亨蒙摹璃辱菲斗胀缘派谴抢钳录赛崔人锑鹤童问亚权笑Fast_SystemC_EngineFast_SystemC_Engine,Acyclic Scheduling,Add signal dependency information Build a signal dep
9、endency graph Assume that no true combinational cycle exists Find best (static) order of signals Schedule processes accordingly Fall-back for graph cycles: dynamic SystemC scheduling Better performance by compiling the schedule,Signal Schedule,S1,S2,S3,S4,S5,A D,Process Schedule,Signal Update,B,C,B,
10、S1,S3,S4,S5,S2,A,B,C,D,Module,Process,Signal,Data Flow Dependency,with dependency info,Final Schedule,匡顿骚表厂辛脖搓桌嗓作赊夹判为左邯卫警鹅苗勘留溃鸟础帧由赶划庞昌Fast_SystemC_EngineFast_SystemC_Engine,Implementing signal dependencies,SC_CTOR(moduleB) SC_METHOD(B); sensitive inReq inAck; outReq(inReq); outAck(inAck); void B() o
11、utReq = inReq; outAck = inAck; ,Module B Source Code,Combinational Processes I/O dependency,B,inAck,outAck,inReq,outReq,S5,S3,S1,Extended syntax to specify dependencies Informations remains local to the module,C,outAck,inReq,inReady,S4,S2,Module C Source Code,SC_CTOR(moduleC) SC_METHOD(C); sensitive
12、 inReq inReady; outAck(inReq); outAck(inReady); void C() outAck = inReq ,S5,B,C,迂受选桅钞蚜漂凛捎香母防履税静绦狡溃嘉沿诉黔推荣撞唯华跑靠端劫缩Fast_SystemC_EngineFast_SystemC_Engine,Experimental results,Tested on two simulators: A 5-stage RISC processor simulator A superscalar processor simulator 10 million simulated instructions
13、 Pentium IV 2 Ghz From 1.96 to 3.56 speedup over SystemC 2.0.1 Wakeups decreased by 29.9 % and 22.7 % Maximum # Delta Cycles decreases from 12 to 3,Wakeup distribution,Performance,# Wakeups,瞅锄篱鲤佛诺撬溉葱遵作止咐凋遥胡唐持兴如凉鞋逻宴或堡飘撰禹艇稍桩Fast_SystemC_EngineFast_SystemC_Engine,Conclusions,FastSysC: Improved software
14、 implementation Improved scheduling algorithm Significant speedup on cycle-accurate simulators Compatible with any SystemC simulator using modules and signals Freely available at www.microlib.org Future Work: Support for additional SystemC communication syntax (events, channels,) Automatic generatio
15、n of signal dependencies Part of a broad effort on simulation (MicroLib): Library of cycle-accurate processor simulators & processor component simulators Generic instruction-set simulators Fast simulation techniques,瀑牟枯容臃骆恶性呐渠锥空历漱淘呆贿篷缔拒号毒矢芝安聘筑独耕稳字绽Fast_SystemC_EngineFast_SystemC_Engine,Q & A,底挛贱鲤谤特敞影棕仔醉约么什愈蔬马珐衔挺箱耿褐宫迟亮扰竞拾砖坏支Fast_SystemC_EngineFast_SystemC_Engine,