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1、.VHDL语言实例例1：设计一七段显示译码器，用它来驱动七段发光管LED显示十六进制数字0到9和字母A到F。LED显示数码管为共阳极。LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY HEX2LED IS PORT( HEX :IN std_logic_vector(3 DOWNTO 0); LED : OUT std_logic_vector(6 TO 0) ); END HEX2LED; 图例1 七段显示译码器实体 ARCHITECTURE HEX2LED_arc OF HEX2LED IS BEGIN - HEX-TO-SEVEN-SEG
2、MENT DECODER - SEGMENT ENCODING - 0 - - - 5 | |1 - - -6 - 4 | |2 - - - 3 精品.WITH HEX SELECT LED= 1111001 when 0001, 0100100 when 0010, 0110000 when 0011, 0011001 when 0100, 0010010 when 0101, 0000010 when 0110, 1111000 when 0111, 0000000 when 1000, 0010000 when 1001, 0001000 when 1010, 0000011 when
3、1011, 1000110 when 1100, 0100001 when 1101, 0000110 when 1110, 0001110 when 1111, 1000000 when others;END HEX2LED_arc;精品. 例2：设计一个八选一数据选择器1）s是通道选择信号, d0,d1,d2,d3,d4,d5,d6,d7数据输入 out1是数据输出ENTITY sels IS PORT(d0,d1,d2,d3,d4,d5,d6,d7:IN BIT; s :INTEGER RANGE 0 TO 7; out1 :OUT BIT);END sels;图例2（a) 八选一数据选
4、择器实体ARCHITECTURE sels_arc OF sels ISBEGIN WITH s SELECT out1 = d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3, d4 WHEN 4, d5 WHEN 5, d6 WHEN 6, d7 WHEN 7;END sels_arc;精品.2)A,B,C是通道选择信号, I0,I1,I2,I3,I4,I5,I6,I7数据输入 Q是数据输出LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7
5、,A,B,C:IN std_logic; Q :OUT std_logic);END mux8; 图例2（b) 八选一数据选择器实体ARCHITECTURE mux8_arc OF mux8 IS SIGNAL sel :INTEGER ；BEGIN Q = I0 AFTER 10 ns WHEN sel= 0 ELSE I1 AFTER 10 ns WHEN sel= 1 ELSE I2 AFTER 10 ns WHEN sel= 2 ELSE I3 AFTER 10 ns WHEN sel= 3 ELSE I4 AFTER 10 ns WHEN sel= 4 ELSE I5 AFTER 1
6、0 ns WHEN sel= 5 ELSE I6 AFTER 10 ns WHEN sel= 6 ELSE I7 AFTER 10 ns ;精品. sel = 0 WHEN A= 0 AND B= 0 AND C= 0 ELSE 1 WHEN A= 1 AND B= 0 AND C= 0 ELSE 2 WHEN A= 0 AND B= 1 AND C= 0 ELSE 3 WHEN A= 1 AND B= 1 AND C= 0 ELSE 4 WHEN A= 0 AND B= 0 AND C= 1 ELSE 5 WHEN A= 1 AND B= 0 AND C= 1 ELSE 6 WHEN A=
7、0 AND B= 0 AND C= 1 ELSE 7;END mux8_arc;例3：设计一D触发器d是输入端，clk是时钟信号控制端，q是触发器的输出端。其程序如下：LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY reg IS PORT(d,clk:IN BIT; q:OUT BIT);END reg;精品.图例3 D触发器实体ARCHITECTURE reg_arc OF reg IS BEGIN PROCESS BEGIN WAIT UNTIL clk= 1; q = d; END PROCESS; PROCESSEND reg_arc;
8、例4：设计一基本RS触发器r、s为触发器的输入信号，q、not_q为触发器的输出信号。LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY RSFF IS PORT(r,s:IN BIT; q,not_q:OUT BIT);END RSFF;图例4 基本RS触发器实体精品.ARCHITECTURE RSFF_arc OF RSFF IS BEGIN PROCESS(r,s) VARIABLE last_state:BIT:= 0; BEGIN ASSERT NOT(r= 1 AND s= 1) REPORT “Both r AND s equal t
9、o 1” SEVERITY error; IF r= 0 AND s= 0 THEN last_state:= last_state ; ELSIF r= 1 AND s= 0 THEN last_state:= 0; ELSE - r= 0 AND s= 1 last_state:= 1; END IF; q = last_state AFTER 10 ns; not_q = NOT(last_state) AFTER 20 ns; END PROCESS;END RSFF_arc;当r和s同时等于1时，触发器处于不定状态。程序设计中设置了断言语句是为了判断r和s都等于1时，输出终端将显示报
10、告“Both r AND s equal to 1”，同时终止模拟过程，并显示错误的严重error，以便设计者调试和修正模块程序。从IF到END IF是条件语句，用到了可选项ELSIF和ELSE来判别RS触发器的其它三种情况。IF语句后面是一赋值语句，将IF语句中赋值的中间变量lsat_state经10 ns后送到q端。图8-12是RS触发器的逻辑电路图。精品.例5：设计一个带有异步清零、同步置数、使能控制的四位二进制计数器LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY COUNT2 IS PORT(A: IN INTEGER RANGE 0 T
11、O 3; CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; EN: IN STD_LOGIC; LD: IN STD_LOGIC; Cout: OUT INTEGER RANGE 0 TO 3 );END COUNT2;图例5 四位二进制计数器实体ARCHITECTURE COUNT2_arc OF COUNT2 IS SIGNAL SIG: INTEGER RANGE 0 TO 3;BEGIN PROCESS (CLK, CLR) BEGIN IF CLR = 0 THEN SIG = 0; ELSIF (CLKEVENT AND CLK = 1) THEN IF
12、LD = 1 THEN SIG = A; ELSE IF EN = 1 THEN SIG = SIG + 1; ELSE SIG = SIG; END IF; END IF; END IF; END PROCESS; Cout = SIG;END COUNT2_arc精品.例6：设计一个存储容量为288的RAM。精品.CS为RAM的片选信号，WR为RAM的写信号，RD为RAM读信号，ADR：八位地址信号，Din：八位数据输入线，Dout为八位数据输出线。library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_unsigned.al
13、l;entity RAM is port (WR: in STD_LOGIC; RD: in STD_LOGIC; ADR: in STD_LOGIC_VECTOR (7 downto 0); CS: in STD_LOGIC; Din: in STD_LOGIC_VECTOR (7 downto 0); Dout: out STD_LOGIC_VECTOR (7 downto 0) );end RAM;图例6 RAM实体architecture RAM_arch of RAM is subtype word is std_logic_vector(7 downto 0); type memo
14、ry is array (0 to 15)of word; signal adr_in:integer range 0 to 15; signal sram:memory; begin adr_in=conv_integer(ADR); process(wr)begin if(wrevent and wr=1)then if(cs=1and wr=1)then sram(adr_in)=din after 2 ns; end if; end if; end process; process(rd,cs)begin if(rd=0and cs=1)then dout=sram(adr_in)af
15、ter 3 ns; else dout next_state=yellow; red_light=0; green_light=1; yellow_light red_light=1; green_light=0; yellow_light=0; if(sensor=1)then next_state=green; else next_state red_light=0; green_light=0; yellow_light=1; next_state=red; end case; end process; process begin wait until clockevent and cl
16、ock=1; present_state=next_state; end process;end abc;精品.该状态机由两个进程描述，第一计算下一个状态逻辑，第二个锁存下一个状态到当前状态。例8：用VHDL设计一家用告警系统的控制逻辑，告警系统有来自传感器的三个输入信号smoke、door、water和准备传输到告警设备的三个输出触发信号fire_alarm、burg_alarm、water_alarm以及使能信号en和alarm_en。VHDL程序描述如下：LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY alarm IS PORT(smoke
17、,door,water:IN std_logic; en,alarm_en :IN std_logic; fire_alarm,burg_alarm:OUT std_logic; water_alarm:OUT std_logic);END alarm;图例8 家用告警系统的控制逻辑电路图 ARCHITECTURE alarm_arc OF alarm ISBEGIN PROCESS(smoke,door,water,en,alarm_en) BEGIN IF (smoke= 1) AND (en= 0) THEN fire_alarm = 1; ELSE fire_alarm = 0; EN
18、D IF; IF (door= 1) AND (en= 0) AND (alarm_en= 0) THEN burg_alarm = 1; ELSE burg_alarm = 0; END IF; IF (water= 1) AND (en= 0) THEN water_alarm = 1; ELSE water_alarm = 0; END IF; END PROCESS;END alarm_arc;精品.程序中用了三个分开的IF语句描述其功能，它们都没有ELSIF关键字，可以看出每个IF语句描述了一个输出端口。第一个IF语句是检测有没有烟雾报警情况，有烟雾火警灾情发生立即产生报警信号，触发fire_alarm。第二和第三IF语句检测不同的报警信号，和第一句相仿。精品.此模块的输入端口有两个使能信号，en使所有的输入都能到达输出，而用alarm_en端口，只对防盗告警系统使能。需要指出的是这种功能很容易用逻辑方程描述，如前面的并行行为程序的例子。但是有时IF语句的形式是更可读、更容易理解。图8-11给出了报警控制逻辑电路图。返回如有侵权请联系告知删除，感谢你们的配合！精品