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1、 PAM8406 EVB User Guide Power Analog Microelectronics, Inc. Rev. V1.0 Nov. 2011 1 PAM8406 EV board User Guide AE Department 1. Revision Information Date Revision Description Comment 2011/11/25 V1.0 Initial release 联系：1 3 6 5 2 4 3 7 5 2 1 柯R 2 0 11. 12 . 2 3 深圳龙创威电子有限公司 PA M 原厂指定代理商 PAM8406 EVB User
2、 Guide Power Analog Microelectronics, Inc. Rev. V1.0 Nov. 2011 2 2. EV Board Schematic +OUT-L 1 PGND-L 2 -OUT-L 3 PVDD-L 4 MUTE 5 VDD 6 INL 7 VREF 8 MODE 9 INR 10 GND 11 SHDN 12 PVDDR 13 -OUT-R 14 PGND-R 15 +OUT-R 16 U1 J4 C5 C1 C2 C3 C7 C4 C8 R1 R2 C6 SD Mute Mode FB1 FB2 FB3 FB4 C10 C9 C12 C11 SP1
3、 SP2 1 2 3 J1 Mode 1 2 3 J2 SD 1 2 3 J3 Mute SDM uteM ode VDD VDDVDDVDD VDD VDD R3 1 2 J5 +C13 PAM8406 Figure 1 Demo Board Schematic 3. PAM8406 Demo Board Description PAM8406 demo board is design for PAM8406 demo and evaluation, targeted to be used in providing a simple and convenient evaluation env
4、ironment for the PAM8406. Requires parts, potentiometer for standard RCA jacks for audio inputs, pin jacks for power supply and signal outputs, low-pass RC output filter for each channel, etc. on the board make it easy to be evaluated. PAM8406 EVB User Guide Power Analog Microelectronics, Inc. Rev.
5、V1.0 Nov. 2011 3 4. EV Board View Figure 2 Demo Board Top View EV board operational sequence : a. Preset the power supply to between 2.5V and 5.5V. b. Connect power supply to EV board power. c. Connect audio input from audio input jack. d. Connect the SPKs to the output jack. e. Turn on the power su
6、pply and verify that the sound quality of speaker. Audio Input Power in: 2.5V5.5V L- channels Output Class D /Class AB select Shutdown select Jump Mute select Jump R- channels Output PAM8406 EVB User Guide Power Analog Microelectronics, Inc. Rev. V1.0 Nov. 2011 4 EV Board BOM List Item Value Type Ra
7、ting Description C7,C8 10uF X5R/X7R, Ceramic/0805 10V PVDD main decoupling CAP C3,C4 1uF X5R/X7R, Ceramic/0603 10V PVDD coupling CAP C6 1uF X5R/X7R, Ceramic/0603 10V VDD decoupling CAP C5 1uF X5R/X7R, Ceramic/0603 10V Vref bypass CAP C1,C2, 1uF X5R/X7R, Ceramic/0603 10V Input coupling CAP R1,R2 10K
8、0805 1% Input Resistor R4 10 0805 5% Separate AVCC from PVDD C13 220uF Electrolytic 10V DC coupling CAP FB1,FB2,FB3,FB4 2A/120 0805 C9,C10,C11,C12, 220pF X5R/X7R, Ceramic/0603 10V For EMI 5. External Components Selection Power Supply decoupling Caps (C3, C4, C6, C7, C8) (1). Low ESR for good THD, PS
9、RR (2).C3,C4 and C6, 1.0uF ceramic for higher frequency transients, spikes (3).C7 and C8, Additional 10uF or greater for low frequency noise filtering and serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs (4).Need place very closed to t
10、he IC PAM8406 EVB User Guide Power Analog Microelectronics, Inc. Rev. V1.0 Nov. 2011 5 Input Capacitors (C1, C2) (1). Form a high pass filter with Ri, and the cut off frequency is fc=1/2Ri*Ci (2). Low leakage current needed, ceramic recommend Input Resistors (R1, R2) (1) Limit the closed-loop gain (
11、2) Form a high pass filter with Ci, and the cut off frequency is fc=1/2*Ri*Ci (3) 1% tolerance needed for resistor matching to improve CMRR, PSRR VREF Bypass Capacitor (C5) (1). 1uF ceramic recommend (2). Need place very closely to the pin for good THD, PSRR EMI Eliminate Filter (FB1, FB2, FB3 and F
12、B4) (1) High impedance at high frequency and very low impedance at low frequency (2) The current rating is higher than 2A 6. PCB Layout Guidelines Grounding (1). Use plane grounding or separate grounds (2). Do not use one line connecting power GND and analog GND (3). Output noise grounds must tie to
13、 system ground at the power in exclusively. (4). Signal currents for the inputs need to be returned to quite ground. This ground only ties to the signal components and the GND pin. Others (1) The power supply de coupling capacitors need to place very close to the PAM8406s pins. (2) The output route should be far away from audio input route. PAM8406 EVB User Guide Power Analog Microelectronics, Inc. Rev. V1.0 Nov. 2011 6 7. PCB Layout Example Fig-3 Top layer Fig-4 Bottom layer