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1、/*程序名称： AD_TLC549实验*主要功能： 将测量的电压值显示在LCD1602上*说 明：*作 者： JZHG*时 间： 2012-05-12*版 本： JZHG-V2.3 */ module Top_Module ( clk, rst_n, AD_DO, AD_CS, AD_CLK, RS, EN, DO ); /- / Define PORT input clk; / Clock input rst_n; / Reset input AD_DO; output AD_CS; output AD_CLK; output RS; output EN; output 7:0 DO; /-
2、/ TLC549 Module wire 7:0 AD_data; TLC549_Module U1(.clk( clk ),.rst_n( rst_n ),推荐精选.AD_DO( AD_DO ),.AD_CS( AD_CS ),.AD_CLK( AD_CLK ),.AD_data( AD_data ) );/-/ Data Dispose Modulewire 23:0 data_out;Data_Dispose_Module U2( .clk( clk ), .rst_n( rst_n ), .data_in( AD_data ), .data_out( data_out ) );/-/
3、LCD1602 ModuleLCD1602_Module U3( .clk( clk ),.rst_n( rst_n ),.LCD_data( data_out),.RS( RS ),.EN( EN ),.DO( DO );/-endmodule推荐精选/* * TLC549 Module * */ module TLC549_Module (clk,rst_n,AD_DO,AD_CS,AD_CLK,AD_data ); /- / Define PORT input clk; / Clock input rst_n; / Reset input AD_DO; output AD_CS; out
4、put AD_CLK; output 7:0 AD_data; /- / SET AD CLock reg 5:0 cnt; reg clk_1; always ( posedge clk or negedge rst_n )if ( !rst_n ) begin cnt <= 6'd0; clk_1 <= 1'b0;endelse if ( cnt <= 6'd50 ) cnt <= cnt + 1'b1; / T = 2uselse begin cnt <= 6'd0;clk_1 <= clk_1;end/-/ D
5、elay推荐精选 reg 4:0 T; always ( negedge clk_1 or negedge rst_n )if ( !rst_n ) T <= 5'd0;else T <= T + 1'b1; /- / Read Data reg CS_r; reg CLK_r; reg 7:0 data_r; reg 7:0 BUF; always ( posedge clk_1 or negedge rst_n ) if ( !rst_n ) begin CS_r <= 1'b1; CLK_r <= 1'b0; data_r <
6、= 8'd0; BUF <= 8'd0; end else case ( T ) 0, 1: begin CS_r <= 1'b0; CLK_r <= 1'b0; end 2, 3, 4, 5, 6, 7, 8, 9: begin CLK_r <= 1'b1; data_r0 <= AD_DO; data_r 7:1 <= data_r 6:0 ; end default: begin CS_r <= 1'b1; CLK_r <= 1'b0; BUF <= data_r; end en
7、dcase /- assign AD_CS = CS_r; assign AD_CLK = CLK_r ? clk_1 : 1'b0; assign AD_data = BUF; /- Endmodule推荐精选/* * Data dispose Module * */ module Data_Dispose_Module ( clk, rst_n, data_in, data_out );/-/Define PORT input clk; input rst_n; input 7:0 data_in; output 23:0 data_out; /- / Data * 100 reg
8、 31:0 temp; always ( posedge clk or negedge rst_n )if ( !rst_n ) temp <= 8'd0; else temp <= data_in * 100/( 95 ); /- / Data Dispose reg 31:0 bai; reg 31:0 shi; reg 31:0 ge; always ( posedge clk or negedge rst_n )if ( !rst_n ) begin bai <= 32'd0;shi <= 32'd0;ge <= 32'd0
9、;endelse begin 推荐精选 bai <= temp / 100 + "0" shi <= temp % 100 /10 + "0" ge <= temp % 10 + "0"end /- assign data_out = bai 7:0 , shi 7:0 , ge 7:0 ; /- endmodule /* * LCD1602 Module * */ module LCD1602_Module ( clk,rst_n,LCD_data,RS,EN,DO);/-/ Define PORT推荐精选inpu
10、t clk; / Clockinput rst_n; / Resetinput 23:0 LCD_data;output RS;output EN;output 7:0 DO;/-/ Set LCD1602 Clockreg 15:0 cnt;reg LCD_clk;always ( posedge clk or negedge rst_n )if ( !rst_n ) begin cnt <= 16'd0; LCD_clk <= 1'b0; endelse if ( cnt <= 16'd50_000 ) cnt <= cnt + 1'
11、b1; / T = 2mselse begin cnt <= 16'd0; LCD_clk <= LCD_clk;end/-reg 3:0 i;reg RS_r;reg EN_r;reg 7:0 DO_r;always ( posedge LCD_clk or negedge rst_n )if ( !rst_n ) begin i <= 4'd0;RS_r <= 1'b0;EN_r <= 1'b0;DO_r <= 8'd0;endelse case ( i )/=/ Init LCD 0: begin EN_r &l
12、t;= 1'b1; RS_r <= 1'b0; DO_r <= 8'h38; i <= i + 1'b1; end 推荐精选 1: begin RS_r <= 1'b0; DO_r <= 8'h08; i <= i + 1'b1; end 2: begin RS_r <= 1'b0; DO_r <= 8'h01; i <= i + 1'b1; end 3: begin RS_r <= 1'b0; DO_r <= 8'h06; i &l
13、t;= i + 1'b1; end 4: begin RS_r <= 1'b0; DO_r <= 8'h0C; i <= i + 1'b1; end /= / Write DATA 5: begin RS_r <= 1'b0; DO_r <= 8'h80; i <= i + 1'b1; end / write addr 6: begin RS_r <= 1'b1; DO_r <= LCD_data 23:16 ; i <= i + 1'b1; end / write d
14、ata 7: begin RS_r <= 1'b0; DO_r <= 8'h81; i <= i + 1'b1; end / write addr 8: begin RS_r <= 1'b1; DO_r <= "." i <= i + 1'b1; end / write data 9: begin RS_r <= 1'b0; DO_r <= 8'h82; i <= i + 1'b1; end / write addr 10: begin RS_r <=
15、 1'b1; DO_r <= LCD_data 15:8 ; i <= i + 1'b1; end / write data 11: begin RS_r <= 1'b0; DO_r <= 8'h83; i <= i + 1'b1; end / write addr 12: begin RS_r <= 1'b1; DO_r <= LCD_data 7:0 ; i <= i + 1'b1; end / write data 13: begin RS_r <= 1'b0; DO_r <= 8'h84; i <= i + 1'b1; end / write addr 14: begin RS_r <= 1'b1; DO_r <= "v" i <= 4'd5; end / write data /= endcase/-assign RS = RS_r;assign EN = EN_r ? LCD_clk : 1'b0;推荐精选assign DO = DO_r;/-endmodule （注：可编辑下载，若有不当之处，请指正，谢谢!） 推荐精选