《[工学]基于QUARTUS MODELSIM 仿真.doc》由会员分享，可在线阅读，更多相关《[工学]基于QUARTUS MODELSIM 仿真.doc（60页珍藏版）》请在三一文库上搜索。
1、基于QUARTUS MODELSIM 仿真建立MODELSIM ALTERA库文件在transcript窗键入如下命令即可建立名为cycloneii的modelsim ALTERA仿真文件。vlib cycloneii vmap cycloneii cycloneii vcom -work cycloneii C:/altera/80/quartus/eda/sim_lib/cycloneii_atoms.vhdvcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/cycloneii_components.vhdvcom -work cyc
2、loneii c:/altera/80/quartus/eda/sim_lib/altera_mf_components.vhdvcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/altera_mf.vhd注：220model.vhd 是work.lpm_components本例中名字命名为了cyclone因为原来在D:MODALTcycloneii下编译的quartus的仿真库，所以在新的工程中将库映射到D:MODALTcycloneii，库名为cyclone注意引用仿真库时库名叫cyclone。设计源文件：见附录测试台文件LIBRAR
3、Y cyclone ; LIBRARY ieee ; USE IEEE.STD_LOGIC_SIGNED.ALL;USE cyclone.cycloneii_components.all ; USE ieee.std_logic_1164.all ; ENTITY wave_tb IS END ; - cyclone为MODELSIM中ALTERA库的名称ARCHITECTURE wave_tb_arch OF wave_tb IS SIGNAL dout : std_logic_vector (7 downto 0) ; SIGNAL dac_wr : std_logic ; SIGNAL
4、dac_cs : std_logic ; SIGNAL switch : std_logic_vector (2 downto 0):=000 ; SIGNAL dac_ab : std_logic ; SIGNAL clk : std_logic:=0 ; COMPONENT wave PORT ( dout : out std_logic_vector (7 downto 0) ; dac_wr : out std_logic ; dac_cs : out std_logic ; switch : in std_logic_vector (2 downto 0) ; dac_ab : ou
5、t std_logic ; clk : in std_logic ); END COMPONENT ; BEGIN DUT : wave PORT MAP ( dout = dout , dac_wr = dac_wr , dac_cs = dac_cs , switch = switch , dac_ab = dac_ab , clk = clk ) ; process(clk) begin clk add wave *Vsimrun 140us选择dout信号，选择format-analog，REDIX-UNSIGNED附录：设计源文件LIBRARY IEEE, cyclone;USE I
6、EEE.STD_LOGIC_SIGNED.ALL;USE IEEE.std_logic_1164.all;USE cyclone.cycloneii_components.all;ENTITY wave IS PORT (dac_wr : OUT std_logic;clk : IN std_logic;dac_cs : OUT std_logic;dac_ab : OUT std_logic;dout : OUT std_logic_vector(7 DOWNTO 0);switch : IN std_logic_vector(2 DOWNTO 0);END wave;ARCHITECTUR
7、E structure OF wave ISSIGNAL gnd : std_logic := 0;SIGNAL vcc : std_logic := 1;SIGNAL devoe : std_logic := 1;SIGNAL devclrn : std_logic := 1;SIGNAL devpor : std_logic := 1;SIGNAL ww_devoe : std_logic;SIGNAL ww_devclrn : std_logic;SIGNAL ww_devpor : std_logic;SIGNAL ww_dac_wr : std_logic;SIGNAL ww_clk
8、 : std_logic;SIGNAL ww_dac_cs : std_logic;SIGNAL ww_dac_ab : std_logic;SIGNAL ww_dout : std_logic_vector(7 DOWNTO 0);SIGNAL ww_switch : std_logic_vector(2 DOWNTO 0);SIGNAL inst|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus : std_logic_vector(5 DOWNTO 0);SIGNAL inst|altsyncram_compon
9、ent|auto_generated|ram_block1a0_PORTADATAOUT_bus : std_logic_vector(7 DOWNTO 0);SIGNAL clkclkctrl_INCLK_bus : std_logic_vector(3 DOWNTO 0);SIGNAL inst2|clk1clkctrl_INCLK_bus : std_logic_vector(3 DOWNTO 0);SIGNAL inst4|Add1114_combout : std_logic;SIGNAL inst4|Add1117 : std_logic;SIGNAL inst4|Add1118_
10、combout : std_logic;SIGNAL inst4|Add0357_combout : std_logic;SIGNAL inst4|Add0363_combout : std_logic;SIGNAL inst6|Add060_combout : std_logic;SIGNAL inst6|Add061 : std_logic;SIGNAL inst6|Add062_combout : std_logic;SIGNAL inst6|Add063 : std_logic;SIGNAL inst6|Add064_combout : std_logic;SIGNAL inst6|A
11、dd065 : std_logic;SIGNAL inst6|Add066_combout : std_logic;SIGNAL inst6|Add067 : std_logic;SIGNAL inst6|Add068_combout : std_logic;SIGNAL inst2|Add067 : std_logic;SIGNAL inst2|Add068_combout : std_logic;SIGNAL inst7|Mux0158_combout : std_logic;SIGNAL inst7|Mux154_combout : std_logic;SIGNAL inst7|Mux2
12、54_combout : std_logic;SIGNAL inst6|clk1regout : std_logic;SIGNAL inst4|Add0374_combout : std_logic;SIGNAL inst6|Equal041_combout : std_logic;SIGNAL inst6|clk127_combout : std_logic;SIGNAL inst6|coun83_combout : std_logic;SIGNAL inst6|coun84_combout : std_logic;SIGNAL inst2|coun83_combout : std_logi
13、c;SIGNAL clkclkctrl_outclk : std_logic;SIGNAL clkcombout : std_logic;SIGNAL inst3|q2_combout : std_logic;SIGNAL inst3|qregout : std_logic;SIGNAL inst7|Mux0156_combout : std_logic;SIGNAL inst5|num3312_combout : std_logic;SIGNAL inst5|num0_wirecell_combout : std_logic;SIGNAL inst5|num3313 : std_logic;
14、SIGNAL inst5|num4314_combout : std_logic;SIGNAL inst5|num4315 : std_logic;SIGNAL inst5|num5316_combout : std_logic;SIGNAL inst5|num5317 : std_logic;SIGNAL inst5|num6318_combout : std_logic;SIGNAL inst5|num7322_combout : std_logic;SIGNAL inst5|Equal052_combout : std_logic;SIGNAL inst5|num7323_combout
15、 : std_logic;SIGNAL inst5|num324_combout : std_logic;SIGNAL inst5|num6319 : std_logic;SIGNAL inst5|num7320_combout : std_logic;SIGNAL inst4|LessThan0102_combout : std_logic;SIGNAL inst4|LessThan0103_combout : std_logic;SIGNAL inst4|Add0377_combout : std_logic;SIGNAL inst4|Add0358 : std_logic;SIGNAL
16、inst4|Add0359_combout : std_logic;SIGNAL inst4|Add0376_combout : std_logic;SIGNAL inst4|Add0360 : std_logic;SIGNAL inst4|Add0361_combout : std_logic;SIGNAL inst4|Add0375_combout : std_logic;SIGNAL inst4|Add0362 : std_logic;SIGNAL inst4|Add0364 : std_logic;SIGNAL inst4|Add0365_combout : std_logic;SIG
17、NAL inst4|Add0373_combout : std_logic;SIGNAL inst4|Add0366 : std_logic;SIGNAL inst4|Add0368 : std_logic;SIGNAL inst4|Add0369_combout : std_logic;SIGNAL inst4|Add0371_combout : std_logic;SIGNAL inst7|Mux0159_combout : std_logic;SIGNAL inst7|Mux0160_combout : std_logic;SIGNAL inst7|Mux0157_combout : s
18、td_logic;SIGNAL inst4|Add0367_combout : std_logic;SIGNAL inst4|Add0372_combout : std_logic;SIGNAL inst4|Add1105_cout : std_logic;SIGNAL inst4|Add1107 : std_logic;SIGNAL inst4|Add1109 : std_logic;SIGNAL inst4|Add1111 : std_logic;SIGNAL inst4|Add1113 : std_logic;SIGNAL inst4|Add1115 : std_logic;SIGNAL
19、 inst4|Add1116_combout : std_logic;SIGNAL inst7|Mux155_combout : std_logic;SIGNAL inst7|Mux156_combout : std_logic;SIGNAL inst7|Mux255_combout : std_logic;SIGNAL inst7|Mux256_combout : std_logic;SIGNAL inst7|Mux354_combout : std_logic;SIGNAL inst4|Add1112_combout : std_logic;SIGNAL inst7|Mux355_comb
20、out : std_logic;SIGNAL inst7|Mux356_combout : std_logic;SIGNAL inst4|Add1110_combout : std_logic;SIGNAL inst2|Add060_combout : std_logic;SIGNAL inst2|coun84_combout : std_logic;SIGNAL inst2|Add061 : std_logic;SIGNAL inst2|Add063 : std_logic;SIGNAL inst2|Add064_combout : std_logic;SIGNAL inst2|Add062
21、_combout : std_logic;SIGNAL inst2|Add065 : std_logic;SIGNAL inst2|Add066_combout : std_logic;SIGNAL inst2|Equal041_combout : std_logic;SIGNAL inst2|clk127_combout : std_logic;SIGNAL inst2|clk1regout : std_logic;SIGNAL inst2|clk1clkctrl_outclk : std_logic;SIGNAL inst1|lpm_counter_component|auto_gener
22、ated|counter_comb_bita0combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita0COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita1combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita1COUT : std_logic
23、;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita2combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita2COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita3combout : std_logic;SIGNAL inst1|lpm_counter_component|aut
24、o_generated|counter_comb_bita3COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita4combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita4COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita5combout : st
25、d_logic;SIGNAL inst7|Mux454_combout : std_logic;SIGNAL inst7|Mux455_combout : std_logic;SIGNAL inst7|Mux456_combout : std_logic;SIGNAL inst4|Add1108_combout : std_logic;SIGNAL inst7|Mux0161_combout : std_logic;SIGNAL inst7|Mux515_combout : std_logic;SIGNAL inst7|Mux516_combout : std_logic;SIGNAL ins
26、t4|Add1106_combout : std_logic;SIGNAL inst7|Mux615_combout : std_logic;SIGNAL inst7|Mux616_combout : std_logic;SIGNAL inst7|Mux731_combout : std_logic;SIGNAL inst4|temp0111_combout : std_logic;SIGNAL inst7|Mux732_combout : std_logic;SIGNAL inst5|num : std_logic_vector(7 DOWNTO 0);SIGNAL inst4|temp :
27、 std_logic_vector(7 DOWNTO 0);SIGNAL inst1|lpm_counter_component|auto_generated|safe_q : std_logic_vector(5 DOWNTO 0);SIGNAL inst2|coun : std_logic_vector(4 DOWNTO 0);SIGNAL inst|altsyncram_component|auto_generated|q_a : std_logic_vector(7 DOWNTO 0);SIGNAL switchcombout : std_logic_vector(2 DOWNTO 0
28、);SIGNAL inst6|coun : std_logic_vector(4 DOWNTO 0);SIGNAL ALT_INV_clkcombout : std_logic;BEGINdac_wr = ww_dac_wr;ww_clk = clk;dac_cs = ww_dac_cs;dac_ab = ww_dac_ab;dout = ww_dout;ww_switch = switch;ww_devoe = devoe;ww_devclrn = devclrn;ww_devpor = devpor;inst|altsyncram_component|auto_generated|ram_
29、block1a0_PORTAADDR_bus = (inst1|lpm_counter_component|auto_generated|safe_q(5) & inst1|lpm_counter_component|auto_generated|safe_q(4) & inst1|lpm_counter_component|auto_generated|safe_q(3) & inst1|lpm_counter_component|auto_generated|safe_q(2) & inst1|lpm_counter_component|auto_generated|safe_q(1) &
30、 inst1|lpm_counter_component|auto_generated|safe_q(0);inst|altsyncram_component|auto_generated|q_a(0) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(0);inst|altsyncram_component|auto_generated|q_a(1) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(1
31、);inst|altsyncram_component|auto_generated|q_a(2) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(2);inst|altsyncram_component|auto_generated|q_a(3) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(3);inst|altsyncram_component|auto_generated|q_a(4) =
32、inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(4);inst|altsyncram_component|auto_generated|q_a(5) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(5);inst|altsyncram_component|auto_generated|q_a(6) = inst|altsyncram_component|auto_generated|ram_block1a
33、0_PORTADATAOUT_bus(6);inst|altsyncram_component|auto_generated|q_a(7) = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus(7);clkclkctrl_INCLK_bus = (gnd & gnd & gnd & clkcombout);inst2|clk1clkctrl_INCLK_bus = (gnd & gnd & gnd & inst2|clk1regout);ALT_INV_clkcombout 00111100001111
34、11,sum_lutc_input = cin)- pragma translate_onPORT MAP (datab = inst4|temp(5),datad = VCC,cin = inst4|Add1113,combout = inst4|Add1114_combout,cout = inst4|Add1115);inst4|Add1116 : cycloneii_lcell_comb- Equation(s):- inst4|Add1116_combout = inst4|temp(6) & (GND # !inst4|Add1115) # !inst4|temp(6) & (in
35、st4|Add1115 $ GND)- inst4|Add1117 = CARRY(inst4|temp(6) # !inst4|Add1115)- pragma translate_offGENERIC MAP (lut_mask = 0011110011001111,sum_lutc_input = cin)- pragma translate_onPORT MAP (datab = inst4|temp(6),datad = VCC,cin = inst4|Add1115,combout = inst4|Add1116_combout,cout = inst4|Add1117);inst
36、4|Add1118 : cycloneii_lcell_comb- Equation(s):- inst4|Add1118_combout = inst4|temp(7) $ !inst4|Add1117- pragma translate_offGENERIC MAP (lut_mask = 1100001111000011,sum_lutc_input = cin)- pragma translate_onPORT MAP (datab = inst4|temp(7),cin = inst4|Add1117,combout = inst4|Add1118_combout);inst|alt
37、syncram_component|auto_generated|ram_block1a0 : cycloneii_ram_block- pragma translate_offGENERIC MAP (mem_init0 = X7F73665A4E43382E241C140E09050200000103070B11182029333D4854606C7986939FABB7C2CCD6DFE7EEF4F8FCFEFFFFFDFAF6F1EBE3DBD1C7BCB1A5998C80,data_interleave_offset_in_bits = 1,data_interleave_width
38、_in_bits = 1,init_file = sint.mif,init_file_layout = port_a,logical_ram_name = sin:inst|altsyncram:altsyncram_component|altsyncram_vr61:auto_generated|ALTSYNCRAM,operation_mode = rom,port_a_address_clear = none,port_a_address_width = 6,port_a_byte_enable_clear = none,port_a_byte_enable_clock = none,
39、port_a_data_in_clear = none,port_a_data_out_clear = none,port_a_data_out_clock = clock0,port_a_data_width = 8,port_a_first_address = 0,port_a_first_bit_number = 0,port_a_last_address = 63,port_a_logical_ram_depth = 64,port_a_logical_ram_width = 8,port_a_write_enable_clear = none,port_a_write_enable_
40、clock = none,port_b_address_width = 6,port_b_data_width = 8,ram_block_type = M4K,safe_write = err_on_2clk)- pragma translate_onPORT MAP (clk0 = inst2|clk1clkctrl_outclk,portaaddr = inst|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus,devclrn = ww_devclrn,devpor = ww_devpor,portadataou
41、t = inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus);inst4|Add0357 : cycloneii_lcell_comb- Equation(s):- inst4|Add0357_combout = inst4|temp(1) $ GND- inst4|Add0358 = CARRY(!inst4|temp(1)- pragma translate_offGENERIC MAP (lut_mask = 1100110000110011,sum_lutc_input = datac)- pra
42、gma translate_onPORT MAP (datab = inst4|temp(1),datad = VCC,combout = inst4|Add0357_combout,cout = inst4|Add0358);inst4|Add0363 : cycloneii_lcell_comb- Equation(s):- inst4|Add0363_combout = inst4|temp(4) & (inst4|Add0362 # GND) # !inst4|temp(4) & !inst4|Add0362- inst4|Add0364 = CARRY(inst4|temp(4) # !inst4|Add0362)- pragma translate_offGENERIC MAP (lut_mask = 1010010110101111,sum_lutc_input = cin)- pragma translate_onPORT MAP (dataa = inst4|temp(4),datad = VCC