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1、Figure 81 A 2-bit asynchronous binary counter. Open file F08-01 to verify operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 82 Timing diagram for the counter of Figure 81. As in previous chap
2、ters, output waveforms are shown in green.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 83 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F08-03 to verify ope
3、ration.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 84 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearso
4、n Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 85 Four-bit asynchronous binary counter and its timing diagram. Open file F08-05 and verify the operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jer
5、sey 07458 All rights reserved.,Figure 86 An asynchronously clocked decade counter with asynchronous recycling.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 87 Asynchronously clocked modulus-12 coun
6、ter with asynchronous recycling.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 88 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs
7、are internally connected HIGH.),Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 89 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n s
8、tates.),Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 810 74LS93 connected as a modulus-12 counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle Ri
9、ver, New Jersey 07458 All rights reserved.,Figure 811 A 2-bit synchronous binary counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 812 Timing details for the 2-bit synchronous counter operation
10、 (the propagation delays of both flip-flops are assumed to be equal).,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 813 Timing diagram for the counter of Figure 811.,Thomas L. Floyd Digital Fundamen
11、tals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 814 A 3-bit synchronous binary counter. Open file F08-14 to verify the operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River,
12、 New Jersey 07458 All rights reserved.,Figure 815 Timing diagram for the counter of Figure 814.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 816 A 4-bit synchronous binary counter and timing diagra
13、m. Points where the AND gate outputs are HIGH are indicated by the shaded areas.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 817 A synchronous BCD decade counter. Open file F08-17 to verify operat
14、ion.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 818 Timing diagram for the BCD decade counter (Q0 is the LSB).,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. U
15、pper Saddle River, New Jersey 07458 All rights reserved.,Figure 819 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.),Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jers
16、ey 07458 All rights reserved.,Figure 820 Timing example for a 74HC163.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 821 The 74F162 synchronous BCD decade counter. (The qualifying label CTR DIV 10 i
17、ndicates a counter with ten states.),Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 822 Timing example for a 74F162.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.
18、 Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 823 A basic 3-bit up/down synchronous counter. Open file F08-23 to verify operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 8
19、24,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 825 The 74HC190 up/down synchronous decade counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle R
20、iver, New Jersey 07458 All rights reserved.,Figure 826 Timing example for a 74HC190.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 827 General clocked sequential circuit.,Thomas L. Floyd Digital Fun
21、damentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 828 State diagram for a 3-bit Gray code counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights
22、 reserved.,Figure 829 Examples of the mapping procedure for the counter sequence represented in Table 87 and Table 88.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 830 Karnaugh maps for present-sta
23、te J and K inputs.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 831 Three-bit Gray code counter. Open file F08-31 to verify operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pea
24、rson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 832,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 833,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by
25、 Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 834,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 835 State diagram for a 3-bit up/down Gray code counter.,T
26、homas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 836 J and K maps for Table 811. The control input, Y, is treated as a fourth variable.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson
27、 Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 837 Three-bit up/down Gray code counter.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 838 Two cascaded counters (al
28、l J and K inputs are HIGH).,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 839 Timing diagram for the cascaded counter configuration of Figure 838.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright
29、2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 840 A modulus-100 counter using two cascaded decade counters.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,
30、Figure 841 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 842,Thoma
31、s L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 843 A divide-by-100 counter using two 74F162 decade counters.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle
32、 River, New Jersey 07458 All rights reserved.,Figure 844 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by
33、Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 845 Decoding of state 6 (110). Open file F08-45 to verify operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,F
34、igure 846 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Open file F08-46 to verify operation.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 847 A basic decade (BCD) counter and d
35、ecoder.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 848 Outputs with glitches from the decoder in Figure 847. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds
36、wide.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 849 The basic decade counter and decoder with strobing to eliminate glitches.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson E
37、ducation, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 850 Strobed decoder outputs for the circuit of Figure 849.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 851 Simplifie
38、d logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 852 and 853.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 852 Logic diagram of typical divide-
39、by-60 counter using 74F162 synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 853 Logic diagram for
40、 hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 854 Functional block diagram for parking garage
41、 control.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 855 Logic diagram for modulus-100 up/down counter for automobile parking control.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by P
42、earson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 856 Parallel-to-serial data conversion logic.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 857 Example of par
43、allel-to-serial conversion timing for the circuit in Figure 856.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 858 The 74HC163 4-bit synchronous counter.,Thomas L. Floyd Digital Fundamentals, 9e,Cop
44、yright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 859 Example of a failure that affects following counters in a cascaded arrangement.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jerse
45、y 07458 All rights reserved.,Figure 860 Example of a failure in a cascaded counter with a truncated sequence.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 861,Thomas L. Floyd Digital Fundamentals,
46、9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 862,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 863 Traffic light control system block
47、 diagram.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 864 Sequence of traffic light states.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, N
48、ew Jersey 07458 All rights reserved.,Figure 865 Block diagram of the sequential logic.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 866 State diagram for the traffic light control system.,Thomas L.
49、 Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 867 Sequential logic diagram.,Thomas L. Floyd Digital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.,Figure 868