基于FPGA和STM32的FSMC通信.doc

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1、基于FPGA和STM32的FSMC通信1、FSMC简介：FSMC即灵活的静态存储控制器，FSMC管理1GB空间，拥有4个Bank连接外部存储器，每个Bank有独立的片选信号和独立的时序配置；支持的存储器类型有SRAM、PSRAM、NOR/ONENAND、ROM、LCD接口（支持8080和6800模式）、NANDFlash和16位的PCCard。2、在设计中将FPGA当做SRAM来驱动，使用库函数来实现FSMC的初始化配置代码如下：/初始化外部SRAMvoid FSMC_SRAM_Init(void) FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructu

2、re; /定义FSMC初始化的结构体变量 FSMC_NORSRAMTimingInitTypeDef readWriteTIming; /用来设置FSMC读时序和写时序的指针变量 GPIO_InitTypeDef GPIO_InitStructure; /初始化FSMC总线的IO口 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOE|RCC_APB2Periph_AFIO,ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC,ENABLE); /开启FSMC的时钟 GPI

5、O_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_6; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(GPIOE, GPIO_InitStructure); readWriteTIming.FSMC_AddressSetupTIme = 14; readWriteTIming.FSMC_AddressHoldTime = 0x00; readWriteTiming.FSMC_Dat

6、aSetupTime = 16; readWriteTiming.FSMC_BusTurnAroundDuration = 0; readWriteTiming.FSMC_CLKDivision = 0x00; readWriteTiming.FSMC_DataLatency = 0x00; readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStructure.FSMC_Bank=FSMC_Bank1_NORSRAM1; FSMC_NORSRAMInitStructure.FSMC_DataAddressM

7、ux = FSMC_DataAddressMux_Disable; FSMC_NORSRAMInitStructure.FSMC_MemoryType =FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth= FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode=FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity

8、= FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_Write

9、Operation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStr

10、uct = readWriteTiming; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = readWriteTiming; FSMC_NORSRAMInit(FSMC_NORSRAMInitStructure); FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); delay_ms(50)； FPGA代码：/fsmc read / write ep4ce6 demomodule fsmc( ab, /address db, /data wrn, /wr rdn, /rd resetn, /rese

11、tn csn, /cs clk ); input2:0 ab; inout15:0 db; input wrn; input rdn; input resetn; input csn; input clk; reg 15:0 ina = 16d0; /存储数据供ARM读 reg 15:0 inb = 16d1; reg 15:0 inc = 16d2; reg 15:0 ind = 16d3; reg 15:0 ine = 16d4; reg 15:0 inf = 16d5; reg 15:0 ing = 16d6; reg 15:0 inh = 16d7; reg 15:0 outa; re

12、g 15:0 outb; reg 15:0 outc; reg 15:0 outd; reg 15:0 oute; reg 15:0 outf; reg 15:0 outg; reg 15:0 outh; wire rd; wire wr; reg 15:0 indata; assign rd = !(csn rdn); /get rd pulse _|_ assign wr = !(csn wrn) ; /get wr pulse _|_ /*当不进行读写操作时db=indata* *当进行写操作时db=16hzzzz* *当进行读操作时db=indata*/ assign db = rd?

13、 indata:16hzzzz; /write data, 根据地址线选择八个空间写入，每个空间16位 always (negedge wr or negedge resetn) begin if(!resetn)begin outa = 16h0000; outb = 16h0000; outc = 16h0000; outd = 16h0000; oute = 16h0000; outf = 16h0000; outg = 16h0000; outh = 16h0000; end else begin case (ab) 3b000:outa = db; 3b001:outb = db;

14、3b010:outc = db; 3b011:outd = db; 3b100:oute = db; 3b101:outf = db; 3b110:outg = db; 3b111:outh = db; default:; endcase end end /red data 根据地址线选择8个空间读取，每个空间 16位 always (rd or !resetn) begin if(!resetn)indata = 16h0000; else begin case (ab) 3b000:indata = ina; 3b001:indata = inb; 3b010:indata = inc; 3b011:indata = ind; 3b100:indata = ine; 3b101:indata = inf; 3b110:indata = ing; 3b111:indata = inh; default:; endcase end end endmodule

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