《ClassAB_Output_Driver_Design-.pdf》由会员分享，可在线阅读，更多相关《ClassAB_Output_Driver_Design-.pdf（49页珍藏版）》请在三一文库上搜索。
1、1 OUTPUT AMPLIFIERS Analog and Mixed Signal Center, TAMU ECEN 607 (ESS) Material partially provided by Vijayakumar Dhanasekaran 2 The main goal of an output amplifier, also called driver amplifier, is to efficiently drive signals into an output load. The output load typically consists of small resis
2、tor ( 50-100) and a large capacitor ( 5-1000pf) The primary objective of the CMOS output amplifier is to function as a current transformer. Conventional requirements of an output amplifier are: 1. Be efficient; 2. Provide sufficient output power in the form of current or voltage; 3 Avoid signal dist
3、ortion; 4. Provide protection from abnormal conditions (over temperature, short circuit, etc.) 3 Outline 1. Introduction to Drivers 1.1 What is a driver 1.2 Application examples 1.3 Crest factor and its implication to power efficiency 2. Class-AB amplifier design 2.1 Class-AB interpretation and prop
4、erties 2.2 Floating current mirror biasing 2.3 Design example (100ohms driver) 2.4 Low-voltage biasing scheme 3. Compensation of Class-AB amplifiers 3.1 Piece-wise modeling of class-AB stage 3.2 NMC driver design example 4. Practical issues 4.1 Mismatch effects, Load variation, Effect of parasitic r
5、esistance, Process and temperature variation 4 What is a Driver ? Very importantMostly non-criticalPower efficiency DSL/Ethernet line driver, speaker driver Fixed gain, PGA, active filter Application examples Off-chipOn-chip Location of load Small R sometimes along with Large C Small-medium C and la
6、rge R Typical load Designed for wide range of loads Designed for fixed load condition Stability LargeSmallPower delivery Driver AmplifierTypical Amplifier Drivers are amplifiers that interface with external world 5 Application Examples 1. DSL Line driver Drives phone line through a transformer 8 loa
7、d (drives 100ohms phone line through 1:3.54 transformer) Max swing = 4.4Vpp differential Crest Factor = 6.3 RMS Power delivered = -12dBm Signal Bandwidth 1.104MHz THD 80dB LDTo splitter 1:3.54 100 8 6 Application Examples continued 2.Speaker driver Drives speaker/headset loads 16ohms resistive load
8、100pF to 1nF capacitive load Max swing = 2V Crest Factor = 10 RMS Power delivered = 625W THD 90dB PA 16 7 8 ISDN 8 ADSL, VDSL 8 HDSL 8 Cable modem Digital Filter D to A Converter Low Pass filter Line Driver A to D Converter Anti Aliasing Filter VGA Digital Filter Hybrid Tx Rx DSP 3 Analog Video Line
9、 Driver Amplifier 8 8 Set top box 8 Security surveillance 8 Personal Video recorders Video Camera Display Twisted-Pair line NTSC Video Signal Line Driver Line Reciever 9 8High output swing Line attenuation erl Crest factor f dBm Vsupply t V 8 Linearity BER requirements Multi-tone transmission f1f22
10、f2 - f12 f1 - f2 f dBm IM3 f dBm f3 MTPR 8Bandwidth Application specific 8Matching Avoid signal reflections 8Power Efficiency Battery back-up & cooling Requirements 10 Crest factor and power efficiency of amplifiers “Real world” signals have amplitude distribution that is very different from that of
11、 a sine-wave (typical test signal) Peak signal voltage and current is much greater than RMS Consequences of large Crest factor (CF) for amplifiers Large supply voltage for given power delivered Large bias current Huge “stand-by” powerMuli-tone DSL signal in time domain with crest factor of 6 Solutio
12、n: Dynamically change the supply voltage and/or bias current of the amplifier Crest Factor is defined as the peak to RMS ratio of the signal 11 Crest factor and power efficiency Contd Class-G amplifiers save power by switching between multiple supplies depending on signal level K.Maclean et al., “A
13、610-mW zero-overhead class-G full-rate ADSL CO line driver,” IEEE J. Solid-State Circuits, Vol. 38, no. 12, pp. 2191-2200, Dec 2003 Block diagram of Class-G switching scheme presented in Drawbacks Need multiple power supplies, which is not attractive for portable devices Need peak prediction logic i
14、n digital. A memory array and possibly a digital filter Switching could lead to interference problems 12 Crest factor and power efficiency Contd Class-AB biasing is most commonly used to improve power efficiency Current drawn from supply is mostly signal dependant A simple analysis Power delivered =
15、 Power efficiency = Power delivered / Average Power dissipation RCF Vp 2 2 Avg. Power dissipation Class-A Power efficiency Class-ABClass-B 2 CF2 1 R Vp2 2 R*CF Vp2 CF 1 Q VpI R*CF Vp 2 2 + + Ip I CFCF Q 21 1 where Vp is peak output voltage, R is load resistance, CF is crest factor, Ip is peak curren
16、t to load and IQis bias current under quiescent condition 13 Class B Vs Class AB Although a Class-B output stage seems to be more efficient, Class-AB is preferred in practice Large GBW is required to linearize the “cross over distortion” associated with Class-B output stage For Class-AB, minimizing
17、IQ/IP improves output stage efficiency but GBW requirement and associated power must be kept in mind Spending some power in linearizing the output stage can potentially result in an overall efficient solution Output Stage Gain Stage Output Stage Gain Stage Large Bandwidth system Moderate Bandwidth s
18、ystem Vo Vo Vin Vin Class-B Class-AB 14 An apparent paradox with push-pull stage The output resistance of a common- drain transistor is 1/gm while that of common-source transistor is 1/gds Why is the common-source output stage used for drivers even if the swing requirement is relaxed ? M1 M2 Vo M1 M
19、2 Vo a)b) CD - output stage CS - output stage The output impedance is mainly determined by 1/(Agm) where A is gain of the high-gain stage and gm is transconductance of the output stage Common-drain stage performs better as a buffer by itself but is not preferred in closed loop amplifiers Common-sour
20、ce output stage is assumed for rest of this presentation A High Gain Stage Vin goAgm 1 Zo + = + = gm Output Stage Vo 15 CLASS-ABOUTPUT STAGE DESIGN ?Class-AB interpretation and properties ?Floating current mirror biasing ?Design example (100ohms driver) ?Low-voltage biasing scheme VV v P Efficiency
21、SSDD OUT SUPPLY PRL = 2 Class-AB () 2 )( 2 V V v P Efficiency SS DD peakOUT SUPPLY PRL =Class-B 16 Class AB output stage interpretation IM2 IM1 Imin VIN I IO (Class-AB) IO (Class-B) IQ -IQ -Imin Start with a class-B amplifier with input Vin biased such that Vgs = Vin + VT If Vgs gets smaller due to
22、process variation and mismatch, there could be “dead zone” in which Io = 0 This problem is alleviated by shifting the current curves using fixed bias current (IQ) In the region |Vin| Vx () 2 VxVin*)Vin(signIo+ Shift the +ve part of red curve to left by Vx and the ve part of red curve to right by Vx
23、and add them together to get the green curve () 2 Vin*)Vin(signIo 17 Desired Properties of class-AB bias Circuit 1.Set the current of both NMOS and PMOS (to IQ) under quiescent condition 2.Limit the minimum current of the weakly conducting device (to Imin) 3.Allow maximum possible voltage swing at t
24、he gate of strongly conducting device 18 Class-AB bias circuit Introduced by Monticelli Transistor M3,4 acts as a “floating current mirror” Biasing is based on Quadratic translinear principle (QTL) Vgs5+Vgs6 = Vgs1+Vgs3 If = K1* and = K2* then IQ= K2*Ib W. Gai, H. Chen, E.Seevinck, “Quadratic-transl
25、inear CMOS multiplier-divider circuit,” Electron. Lett., vol. 33, Issue 10, pp. 860-861, 8 May 1997 3 L W 6 L W 1 L W 5 L W VSS VDD M1 M2 M3 M4 M5 M6 M8 M7 Ib Ib 2*K1*Ib Vo 2*K1*Ib Pbias Nbias IQ Monticellis Class-AB biasing scheme D. M.Monticelli, “A quad CMOS single-supply opamp with rail-to-rail
26、output swing,” IEEE J. Solid-State Circuits, vol. SSC-21, pp. 1026-1034, Dec. 1986 19 Bias circuit operation Nonlinear circuit that has good class-AB properties Signal current is accepted at the source node of M3 and/or M4 Under Q condition, M3 and M4 are designed such that gm3=gm4 With gm3 = gm4, t
27、he floating current mirror acts like a level shifting voltage source with series resistance 1/gm3,4 For large overdrive of M1(2), M3(4) turns off and M4(3) acts as a cascode transistor The cascode transistor serves to pin down the minimum current flowing through the weakly conducting transistor to I
28、min When M1 is weakly conducting, Vg3 Vss = Vgs3max + Vgs1min When M1 is strongly conducting, Vgs1max = Vdd - Vss - VdsatIB 20 Behavior of floating current mirror across output voltage levels M2 M1 VSS VDD VSS VDD M1 M2 M3 M4 off Cascode VSS VDD M1 M2 M3 M4 Vo off Cascode 1/gm3,4 Vo Vo Vo Strong Wea
29、kStrong Weak 21 Design Example 100 driver Specifications Output swing = +/- 2V Supply voltage = +/- 2.5V GBW = 180MHz THD with 1MHz, 2Vpp sine-wave 30dB Full power bandwidth 10MHz Technology = 0.5m Extreme swing condition Vdsat = 0.5V rds not relevant L = 1.0um Calculate W check using simulator if W
30、/L is sufficient to provide Ipeak mAI R Vp I min L O 21=+= Calculate Vgs of M1 under Q and peak swing condition Quiescent state Vg3 Vss = Vgs3Q + Vgs1Q Weakly conducting state Vg3 Vss = Vgs3max + Vgs1min Use this to set the minimum current drawn by M1 22 100 driver Circuit Diagram 2 x (31.6/1)M7 8 x
31、 (2.8/1)M6 2 x (10.3/1)M5 25 x (5.7/1)M4 25 x (2.4/1)M3 125 x (31.6/1)M2 125 x (10.3/1)M1 100 RL 1.5pFCc 12K Rc 12 x (28.5/1)M12,13 1 x (6/1)M10,11 1 x (119/2.2)M9 8 x (5.7/1)M8 VSS VDD M3 M4 M5 M6 M8 M7 Ib 2*K1*Ib Ib Pbias Nbias M1 M2 Vo IT VinpVinm M9M10M11 M12M13 GND RL RCCC RCCC 23 Open Loop Sim
32、ulation Results Vo versus Vi transfer curvedVo/dVi versus Vi curve The characteristic shape of the gain curve (dVo/dVi versus Vi) is a reflection of different regions of operation of output transistors Around Vi = 0, the output transistors are in weak inversion/sub-threshold and saturation region. G
33、ain increases with Vi due to higher current drawn with increasing swing Increase in Vi beyond certain point pushes the output transistors in triode region, which result in sharp fall in the gain 24 Open Loop Simulation Results Contd M1,2 currents versus ViVgs1,2 versus Vi The current curves shows an
34、 IQ 4mA. A modest IQ/IP(1/5) is used. Iminis set to about 1mA. Note that Iminis not maintained when the amplifier is driven in saturation (Vi +/- 40V) Gate voltage plot reflects the non-linear control due to bias circuit 25 Closed loop simulation with Gain=-10 Vo versus Vi The current curves are lin
35、ear with respect to Vi at high swing levels For small swings, the sum of currents of M1 and M2 is linear versus Vi M1,2 current versus Vi 26 Loop Gain AC response for Gain = -10 AC response (inverting gain = 10) Unity gain bandwidth 17.6MHz (due to feedback factor of 1/10) Stability must be verified
36、 for entire output swing range Miller compensation around 2ndstage is employed (pole at the output of 3rdstage is neglected) In this example, the amplifier is treated as a 2 stage amplifier. However, more advanced compensation scheme is required for 3 stage designs 27 Transient simulation result for
37、 Gain=-10 case Output spectrum for 1MHz +/-1V output Second harmonic would be suppressed in a differential version of this amplifier Better linearity can also be achieved with higher GBW but requires more advanced compensation schemes (discussed later) 28 Step Response “Split compensation network” i
38、s used in this amplifier. Rc and Cc is connected between gate of M9 and gates of M1 and M2 This is to ensure symmetric slewing in either direction of swings Splitting the compensation network is also critical to maintain stability across entire swing range 29 Low voltage Class-AB biasing Monticellis
39、 biasing needs min supply of 2VgsM7,8+ VdsatIb Not favorable for low voltage designs in digital CMOS process “Folded mesh biasing”can be used to alleviate this problem Min supply: VdsatM8,9+ VdsatM10,11+ 2*VdsatI2 QTL: Vgs5+Vgs11 = Vgs12+Vgs10 M3-M7 implements minimum selector circuit K. J. de Lange
40、n, J. H. Huijsing, “Compact low-voltage power-efficient operational amplifier cells for VLSI,” IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 14821496, Oct. 1998. Class-AB biasing scheme using folded mesh VSS VDD M1 M2 M3 M5 Vo IQ IREF M4 M6M7 M8M9 M10 M11 M12 I2 I2 30 Operation of Folded Mesh B
41、iasing Assume (W/L)5= (W/L)12 and (W/L)6= (W/L)7 Amplifier consisting of M8-M11 serves to force I5= IREF Quiescent state M6 is in triode region. M4 and M6 together acts like a “composite transistor” with twice the length IQ can be set using the following relation () () () () REFQ I LW LW LW LW II= +
42、= 2 4 1 3 5 2 1 2 1 M1 is strongly conducting M6 is in deep triode region, acting like a closed switch M4 serves to mirror the current through M2 M2 is strongly conducting M4 acts like a cascode device M3,6,7 serves to mirror the current through M1 () () REF I LW LW II= = 2 4 min25 () () REF I LW LW
43、 II= = 1 3 min15 31 COMPENSATION OF CLASS-AB DRIVERS ?Piece-wise modeling of class-AB stage ?NMC driver design example 32 Compensation of Class-AB drivers As mentioned earlier, GBW and the linearity of the output stage determines the overall closed loop linearity of the driver Since GBW is a major f
44、actor in determining stability, we need to analyze the linearity of class-AB stage more closely Due to large power delivery and swing requirements, it is desirable to have the class-AB stage swing near rail-rail Railrail output swing is a major cause of distortion and will be investigated in next fe
45、w slides Linearity spec GBW Power output Supply voltage Compensation 33 Region1 Region2 Region3 IOis the solution of the following quadratic equation where VSUP= VDD-VSS, K=1/2*Kp*W/L, RLis load resistance, Vin and Vx are as already defined Exercise : Derive the above V-I relation for Region 3 and s
46、pecify the range of Vin for which it is valid Piece-wise model for class-AB V-I curve Three distinct operating regions Region1 - Linear versus Vin Region2 - Square law versus Vin Region3 - Parabolic versus Vin Region 1 and 2 were discussed already When the strongly conducting device enter triode reg
47、ion, the third regime of operation (parabolic vs Vin) comes into play KVinVxIO4= () 2 VxVin*)Vin(sign*KIO+= ()()()04221 222 =+ SUPSUPLSUPLOLO VVxVinK/KVRKVRVxVinKIKRI 34 Inferences from the piece-wise model Large gate voltages might be required to supply current when the output stage is in region3 T
48、he distortion due to region3 is typically the limiting factor On the other hand, restriction of operation to region1 and 2 might imply extremely wide output transistors, which could in turn pose compensation problems GBW is determined based on gain required to “linearize” the distortion components due to this Often times, IQ required for compensation (given this GBW) is sufficient to check cross-over distortion Matlab plot of an example piece-wise model MATLAB Po