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1、2设计规则设计规则几何关系定义Width:Sapcing:Extension : 一几何图形内边界到另一图形外边界长度Overlap : 一几何图形内边界到另一图形内边界长度2.2设计规则4M2 lambda =5Mlambda =2.2.1 Well PjvrdlDescriptionSUBMDEEPMinimum width1212Minimum spacing between wells at different potential1818Minimum spacing between wells at same potential66Minimum spacing between we
2、lls of different type002.2.2 Active DescriptionSUBMDEEPMinimum width33Minimum spacing33Source/drain active to well edge66Substrate/well contact active to well edge33Minimum spacing between active of different implant442.2.3 Thick Active is a layer used for those processes offering two differentthick
3、nesses of gate oxide (typically for the layout of transistors that operate at two different voltage levels). The ACTIVE layer is used to delineate all the active areas, regardless of gateoxide thickness. THICK_ACTIVE is used to to mark those ACTIVE areas that will have the thicker gate oxide; ACTIVE
4、 areas outside THICK_ACTIVE will have the thinner gate oxide.RuleDescriptionSUBMDEEPMinimum width44Minimum spacing44Minimum ACTIVE overlap44Minimum space to external ACTIVE44Minimum poly width in a THICK_ACTIVE gate332.2.4 Poly nDescriptionSUBMDEEPMinimum width22Minimum spacing over field33Minimum s
5、pacing over active34Minimum gate extension of active2Minimum active extension of poly34Minimum field poly to active113.5Poly-3.33.4Active2.2.5 Silicide Block 口1pSB width4Minimum SB spacing4Minimum spacing, SB to contact (no contacts allowed inside SB)2Minimum spacing, SB to external active口uMinimum
6、spacing, SB to external poly2Resistor is poly inside SB; poly ends stick out for contacts the entire resistor must be outside well and over fieldN/ApMinimum poly width in resistor5Minimum spacing of poly resistors (in a single SB region)71 Minimum SB overlap of poly22.2.6 Select pDescriptionSUBMDEEP
7、Minimum select spacing to channel of transistor33Minimum select overlap of active22Minimum select overlap of contact1Minimum select width and spacing (Note: P-select and N-selectmay be coincident, but mustnot overlap)24active电A史JiThe same rules apply with N+ Seled and P+_Select reverwd .2.2.7 Electr
8、ode for Capacitor poly2 layer is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polysis the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.RuleDescriptionSUBMDEEPMinimum width7Minimum spacing3Minimum
9、poly overlap5n/aMinimum spacing to active or well edge (not 川ustrated)2Minimum spacing to poly contact6Minimum spacing to unrelated metal22.2.8 Electrode Contact poly2 is contacted through the standardcontact layer, similar to the first poly. The overlap numbers are larger, however.1RulerDescription
10、SUBM-1DEEPExact contact size2 x 2Minimum contact spacing3Minimum electrode overlap (on capacitor)3n/aMinimum electrode overlap (not on capacitor)2Minimum spacing to poly or active3Metali13.4 一T13,22.2.9 Contact to Poly 2.2.10 Contact to Active zqDescriptionSUBMDEEPExact contact size2x22x2Minimum act
11、ive overlapMinimum contact spacing34Minimum spacing to gate of transistor22Active2.2.12 Via 二DescriptionSUBMDEEPMinimum width33Minimum spacing33Minimum overlap of any contact11Minimum spacing when metal line is wider than 10 lambda66ActiveMetallMetallDescriptionSUBMDEEPExact size2 x 23 x 3Minimum vi
12、al spacing33Minimum overlap by metal111Minimum spacing to contact2n/anMinimum spacing to poly or active edge2n/aActive2.2.13 Metal2 pDescriptionSUBMDEEPMinimum width33Minimum spacing34Minimum overlap of via111Minimum spacing when metal line wider than 10 lambda689.1Meta 1292h92bMctal29.3Metal 12.2.1
13、4 Via2 141Metii 13Meta 12DescriptionSUBMDEEPExact size2x23x3Minimum spacing33Minimum overlap by metal21n/aMinimum spacing to via12n/a2.2.14 Metal3 DescriptionSUBMDEEPMinimum width33Minimum spacing to metal334Minimum overlap of via211Minimum spacing when metal line is wider than 10 lambda6815.1Mete 1
14、315.2Via2MThI31 15,32.2.15 Via3 八落3RuleDescriptionSUBMDEEPExact size2x23x3Minimum spacing33Minimum overlap by Metal311M2.2.16 Metal4 RuleDescriptionSUBMDEEPMETAL4 width63METAL4 space64METAL4 overlap of VIA321Minimum spacing when metal line is wider than 10 lambda1282.2.17 CAP_TOP_METAL CAP_TOP_METAL
15、layer is used exclusively for the construction of metal-to-metal capacitors. The bottom plate of the capacitor is one of the regular metal layers, as specified below. CAP_TOP_METAL is the upper plate of the capacitor; it is sandwiched physically between the bottom plate metal and the next metal laye
16、r above, with a thin dielectric between the bottom and top plates.The CAP_TOP_METALan only be contacted from the metal above; the bottom plate metalcan be contacted from below or above (subject, in either case, to rule . CAP_TOP_METAL must always be contained entirely within the bottom plate metal.P
17、rocessBottom PlateTop PlateTop Plate ContactTSMC_025METAL4CAP_TOP_METALVIA4 and METAL5RuleDescriptionLambdaMinimum Width, Capacitor50Minimum Spacing (2 capacitors sharing a single bottom plate)2Minimum bottom metal overlap5Minimum overlap of via3Minimum spacing to bottom metal via5Minimum bottom met
18、al overlap of its via52.2.18 Via4 (DEEP) RuleDescriptionLambdaExact size3 x 3Minimum spacing3Minimum overlap by Metal412.2.19 Metal5 (DEEP)RuleDescription5 Metal Process2.2.20 Overglass that rules in this section are in units of microns. They are not true design rules, but they do make good practice rules. Unfortunately, there are no really good generic pad design rules since pads are process-specific.