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1、INTERNATIONAL STANDARD IEC 61691-2 First edition 2001-06 Behavioural languages Part 2: VHDL multilogic system for model interoperability Reference number IEC 61691-2:2001(E) Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, U
2、ser=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
3、 Consolidated editions The IEC is now publishing consolidated versions of its publications. For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendment 1 and the base publication incorporating amendments 1 and 2. Further in
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6、w.iec.ch) Catalogue of IEC publications The on-line catalogue on the IEC web site (www.iec.ch/catlg-e.htm) enables you to search by a variety of criteria including text searches, technical committees and date of publication. On-line information is also available on recently issued publications, with
7、drawn and replaced publications, as well as corrigenda. IEC Just Published This summary of recently issued publications (www.iec.ch/JP.htm) is also available by email. Please contact the Customer Service Centre (see below) for further information. Customer Service Centre If you have any questions re
8、garding this publication or need further assistance, please contact the Customer Service Centre: Email: custserviec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, User=Wing, B
9、ernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- INTERNATIONAL STANDARD IEC 61691-2 First edition 2001-06 Behavioural languages Part 2: VHDL multilogic system for model interoperability PRICE CODE IEC 2001 Copyright - all rights rese
10、rved No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. International Electrotechnical Commission3, rue de Varemb Geneva, Switzerland Telefax: +41 22
11、919 0300e-mail: inmailiec.ch IEC web site http:/www.iec.ch M For price, see current catalogue Commission Electrotechnique Internationale International Electrotechnical Commission Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/11111110
12、01, User=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- 2 61691-2 IEC:2001(E) INTERNATIONAL ELECTROTECHNICAL COMMISSION _ BEHAVIOURAL LANGUAGES Part 2: VHDL multilogic system for model interoperability FOREWORD 1)The IEC (In
13、ternational Electrotechnical Commission) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-operation on all questions concerning standardization in the electrical and ele
14、ctronic fields. To this end and in addition to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental an
15、d non-governmental organizations liaising with the IEC also participate in this preparation. The IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2)The formal decisions or agree
16、ments of the IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested National Committees. 3)The documents produced have the form of recommendations for international
17、use and are published in the form of standards, technical specifications, technical reports or guides and they are accepted by the National Committees in that sense. 4)In order to promote international unification, IEC National Committees undertake to apply IEC International Standards transparently
18、to the maximum extent possible in their national and regional standards. Any divergence between the IEC Standard and the corresponding national or regional standard shall be clearly indicated in the latter. 5)The IEC provides no marking procedure to indicate its approval and cannot be rendered respo
19、nsible for any equipment declared to be in conformity with one of its standards. 6)Attention is drawn to the possibility that some of the elements of this International Standard may be the subject of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
20、International Standard IEC 61691-2 has been prepared by IEC technical committee 93: Design automation. This standard is based on IEEE Std 1164-1993: Multivalue logic system for VHDL model interoperability The text of this standard is based on the following documents: FDISReport on voting 93/130/FDIS
21、93/140/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This standard does not follow the rules for the structure of international standards given in Part 3 of the ISO/IEC Directives. IEC 61691 consists of the fol
22、lowing parts, under the general title: Behavioural languages: IEC 61691-1:1997, VHDL language reference manual 1) IEC 61691-2:2001, Part 2: VHDL multilogic system for model interoperability _ 1) The edition 2 with the title: VHSIC hardware description languageVHDL (076a) (under consideration) will r
23、eplace it. Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- 61691-2 IEC:2001(E) 3 IEC 61691-3-1,
24、 Part 3-1: Analog description in VHDL (under consideration) IEC 61691-3-2:2001, Part 3-2: Mathematical operation in VHDL IEC 61691-3-3:2001, Part 3-3: Synthesis in VHDL IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration) IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under
25、 consideration) The committee has decided that the contents of this publication will remain unchanged until 2004. At this date, the publication will be reconfirmed; withdrawn; replaced by a revised edition, or amended. Copyright International Electrotechnical Commission Provided by IHS under license
26、 with IECLicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- BEHAVIOURAL LANGUAGES - Part 2: VHDL multilogic system for model interoperatibility 1. Overview 1.1 Scope This standard is embod
27、ied in the Std_logic_1164 package package body along with this clause 1 documentation. The information annex AA is a guide to users and is not part of this standard, but suggests ways in which one might use 1.2 Conformance with this standard The following conformance rules shall apply as they a)No m
28、odifications shall be made to the package declaration b)The Std_logic_1164 package body represents the formal Std_logic_1164 package declaration. Implementers of this package body as it is; or they may choose to implement to the user. Users shall not implement a semantic that 2. Std_logic_1164 packa
29、ge declaration - - Title : Std_logic_1164 multivalue logic system - Library : This package shall be compiled into a library - : symbolically named IEEE. - : - Developers: IEEE model standards group (par 1164) - Purpose : This packages defines a standard for designers - : to use in describing the - :
30、 used in VHDL modeling. - : 61691-2 IEC:2001(E) - 4 - Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS
31、 -,-,- - Limitation: The logic system defined in this package may - : be insufficient for modeling switched - : since such a requirement is out of the - : effort. Furthermore, mathematics, primitives, - : timing standards, etc. are considered - : issues in relation to this package and - : beyond the
32、 scope of this effort. - : - Note : No declarations or definitions shall be - : or excluded from, this package. The - : defines the types, subtypes, and - : Std_logic_1164. The Std_logic_1164 - : considered the formal definition of the - : this package. Tool developers may - : the package body in th
33、e most efficient - : to them. - : - - modification history : - - version | mod. date:| - v4.200 | 01/02/92 | - PACKAGE Std_logic_1164 IS - logic state system (unresolved) TYPE std_ulogic IS ( U, - Uninitialized X, - Forcing Unknown 0, - Forcing 0 1, - Forcing 1 Z, - High Impedance W, - Weak Unknown
34、L, - Weak 0 H, - Weak 1 - - Dont care ); - unconstrained array of std_ulogic for use with the TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE ) OF 61691-2 IEC:2001(E) - 5 - Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, Us
35、er=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- - common subtypes SUBTYPE X01 IS resolved std_ulogic RANGE SUBTYPE X01Z IS resolved std_ulogic RANGE Z) SUBTYPE UX01 IS resolved std_ulogic RANGE 1) SUBTYPE UX01Z IS resolved
36、 std_ulogic RANGE 1, Z) - overloaded logical operators FUNCTION “and” ( l : std_ulogic; r : FUNCTION “nand” ( l : std_ulogic; r : FUNCTION “or” ( l : std_ulogic; r : FUNCTION “nor” ( l : std_ulogic; r : FUNCTION “xor” ( l : std_ulogic; r : FUNCTION “xnor” ( l : std_ulogic; r : FUNCTION “not” ( l : s
37、td_ulogic - vectorized overloaded logical operators FUNCTION “and” ( l, r : std_logic_vector ) FUNCTION “and” ( l, r : std_ulogic_vector ) FUNCTION “nand” ( l, r : std_logic_vector ) FUNCTION “nand” ( l, r : std_ulogic_vector ) FUNCTION “or” ( l, r : std_logic_vector ) FUNCTION “or” ( l, r : std_ulo
38、gic_vector ) FUNCTION “nor” ( l, r : std_logic_vector ) FUNCTION “nor” ( l, r : std_ulogic_vector ) FUNCTION “xor” ( l, r : std_logic_vector ) FUNCTION “xor” ( l, r : std_ulogic_vector ) - - Note : The declaration and implementation of the “ - specifically commented until a time at which the VHDL -
39、officially adopted as containing such a function. At - the following comments may be removed along with this - further “official” balloting of this - the intent of this effort to provide such a function - available in the VHDL standard. - - FUNCTION “xnor” ( l, r : std_logic_vector ) - FUNCTION “xno
40、r” ( l, r : std_ulogic_vector ) FUNCTION “not” ( l : std_logic_vector ) FUNCTION “not” ( l : std_ulogic_vector ) - conversion functions FUNCTION To_bit ( s : std_ulogic; xmap : FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT
41、_VECTOR; FUNCTION To_StdULogic ( b : BIT ) FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN
42、std_ulogic_vector; 61691-2 IEC:2001(E) - 6 - Copyright International Electrotechnical Commission Provided by IHS under license with IECLicensee=IHS Employees/1111111001, User=Wing, Bernie Not for Resale, 03/09/2007 07:28:29 MSTNo reproduction or networking permitted without license from IHS -,-,- -
43、strength strippers and type converters FUNCTION To_X01 ( s : std_logic_vector ) RETURN FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN FUNCTION To_X01 ( b : BIT ) RETUR
44、N X01; FUNCTION To_X01Z ( s : std_logic_vector ) RETURN FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; FUNCTION To_UX01
45、( s : std_logic_vector ) RETURN FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN FUNCTION To_UX01 ( b : BIT ) RETURN UX01; - edge detection FUNCTION rising_edge (SI
46、GNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; - object contains an unknown FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; END Std_logi
47、c_1164; 3. Std_logic_1164 package body - - - Title : Std_logic_1164 multivalue logic system - Library : This package shall be compiled into a library - : symbolically named IEEE. - : - Developers: IEEE model standards group (par 1164) - Purpose : This package defines a standard for designers - : to use in describing the interconnection - : used in VHDL modeling. - : - Limitation: The logic system defined in this package may - : b