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1、 INTERNATIONAL STANDARD IEC 62050 First edition 2005-07 IEEE 1076.6 VHDL Register Transfer Level (RTL) synthesis Reference number IEC 62050(E):2005 IEEE Std. 1076.6(E):2004 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Tech
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9、nsee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:30:09 MDTNo reproduction or networking permitted without license from IHS -,-,- VHDL Register Transfer Level (RTL) synthesis INTERNATIONAL STANDARD IEC 62050 First edition 2005-07 IEEE 1076.6 Commission Electrotechnique Interna
10、tionale International Electrotechnical Commission IEEE 2005 Copyright - all rights reserved IEEE is a registered trademark in the U.S. Patent any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental org
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16、ot be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 62050 has been processed through IEC technical committee 93: Design automation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1076.6 (2004) 93/212/FDI
17、S 93/217/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain un
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38、es into the legal validity or scope of those patents that are brought to its attention. IEC 62050:2005(E) IEEE 1076.6-2004(E) 4 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under licens
39、e with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:30:09 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis Sponsor Design Automation Standards Committee of the IEEE Computer So
40、ciety Approved 25 August 2004 American National Standard Institute Approved 12 May 2004 IEEE-SA Standards Board Abstract: This document specifies a standard for use of very high-speed integrated circuit hard- ware description language (VHDL) to model synthesizable register-transfer level digital log
41、ic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors. Keywords: hardware description language,
42、logic synthesis, register transfer level (RTL), very high- speed integrated circuit hardware description language (VHDL) IEC 62050:2005(E) IEEE 1076.6-2004(E) 5 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. Copyright The Institute of Electrical and Electronics Engineers,
43、Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:30:09 MDTNo reproduction or networking permitted without license from IHS -,-,- This standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subs
44、et of IEC/IEEE 61691-1-1:2004 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain. This standard is based on IEC/IEEE 61691-1-1:2004, IEEE Std 1164TM-1993, and IEEE Std 1076.3TM-1997. The purpose of this standard is to define a syntax and seman
45、tics that can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use IEC/IEEE 61691-1-1:2004 This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of
46、 a particular synthesis implementation by making their designs compliant with this standard. The standard is intended for use by logic designers and electronic engineers. This document specifies IEEE Std 1076.6-2004, which is a revision of IEEE Std 1076.6-1999. The VHDL Synthesis Interoperability Wo
47、rking Group (SIWG) of the IEEE Computer Society started the development of IEEE Std 1076.6-2004 in January 1998. The work initially started as a Level 2 effort (Level 1 being IEEE Std 1076.6-1999). In fact the work on Level 2 continued right after Level 1 was completed by the working group. The work
48、ing group realized that a Level 2 was required and that it would take some time to develop and continued working on it at regular face-to-face meetings and teleconferences. As the Level 2 draft continued to mature, the working group decided that rather than having two different levels of synthe- sis subsets, it was better to just have one standard, with IEEE Std 1076.6-2004 becoming Level 2. The intent of this version was to include a maximum subset of VHDL that could be used to describe synthe- sizable RTL logic. This included considering new features introduced by IEC/IEEE 61691-1-1:2004,