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1、BRITISH STANDARD BS CECC 90104:1981 Incorporating Amendment Nos. 1 and 2 Specification for Harmonized system of quality assessment for electronic components Family specification C. Mos Digital Integrated Circuits Series 4000B and 4000UB Licensed Copy: London South Bank University, London South Bank
2、University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-2000 ISBN 0 580 35805 4 Amendments issued since publication Amd. No.Date of issueComments 5197August 1986 5597April 1987Indicated by a sideline in the margin Licensed Copy: London South Bank Universi
3、ty, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-2000i Contents Page National forewordii Forewordiii Text of CECC 901041 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00
4、2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 ii BSI 03-2000 National foreword This British Standard has been prepared under the direction of the Electronic Components Standards Committee. It is identical with CENELEC Electronic Components Committee (CECC) 90104 Family specification: C.MOS Dig
5、ital integrated circuits Series 4000 B and 4000 UB. This standard is a harmonized specification within the CECC system. Terminology and conventions. The text of the CECC specification has been accepted as suitable for publication, without deviation, as a British Standard. Certain terminology and con
6、ventions are used, however, that are not identical with those used in British Standards. Attention is particularly drawn to the following. The comma has been used throughout as a decimal maker. In British Standards it is current practice to use a full point on the baseline as the decimal marker. Cro
7、ss references. The British Standard harmonized with CECC 00100 is BS E9000 “General requirements for electronic components of assessed quality harmonized with the CENELEC Electronic Components Committee System” Part 1 “Basic rules”. The following International Standards are referred to in the text a
8、nd for each there is a corresponding British Standard; these are listed below. Scope. This Standard lists the general information for ratings, characteristics and inspection requirements for a series of integrated circuits which shall be included as mandatory requirements in detail specifications in
9、 accordance with BS CECC 90000. Detail specification layout. In the event of conflict between the requirements of this specification and the provisions of Section 3 of BS 9000-2 the latter shall take precedence except the front page layout will be in accordance with BS 9000 Circular Letter No. 15. A
10、 British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. International StandardCorresponding Britis
11、h Standard CECC 90000:1976BS CECC 90000:1977 Harmonized system of quality assessment for electronic components: Generic specification: monolithic integrated circuits (Identical) CECC 90100:1976BS CECC 90100:1977 Harmonized system of quality assessment for electronic components: Sectional specificati
12、on: Digital monolithic integrated circuits (Identical) IEC 191-2:1966BS 3934:1965 Dimensions of semiconductor devices (Related) Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, the CECC title page, pages ii to iv, pages 1 to 13 and a back cover. This sta
13、ndard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI Lic
14、ensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 ii BSI 03-2000 Content Page Forewordiii 1Limiting conditions of use for the family1 2Recommended conditions of use and associated characteristics
15、for the family2 3Inspection requirements8 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-2000iii Foreword The CENELEC Electronic Components Committee (CECC) is composed of those membe
16、r countries of the European Committee for Electrotechnical Standardization (CENELEC) who wish to take part in a harmonized System for electronic components of assessed quality. The object of the System is to facilitate international trade by the harmonization of specifications and quality assessment
17、 procedures for electronic components, and by the grant of an internationally recognized Mark or Certificate, of Conformity. The components produced under the System are thereby accepted by all member countries without further testing. This document has been formally approved by the CECC and has bee
18、n prepared for those countries taking part in the System who wish to prepare and issue detail specifications for DIGITAL INTEGRATED CIRCUITS. It should be read in conjunction with document CECC 00100: Basic Rules (1974). At the date of printing of this document the member countries of the CECC are B
19、elgium, Denmark, France, Germany, Ireland, Italy, the Netherlands, Norway, Sweden, Switzerland, the United Kingdom, and copies of it can be obtained from the addressees shown on the inside cover. Preface This family specification was prepared by CECC Working Group 9: Integrated Circuits. It contains
20、 the general information for the C.MOS series 4000 B and 4000 UB. Together with the device type detail specification, usually prepared nationally, it forms the complete detail specification for the device belonging to series 4000 B or 4000 UB. The text of this specification was circulated to the CEC
21、C for voting in the documents listed below and was ratified by the CECC for printing as a CECC specification. DocumentVoting DateReport on the Voting CECC(Secretariat)833November 1979CECC(Secretariat)914 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 G
22、MT+00:00 2006, Uncontrolled Copy, (c) BSI iv blank Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-20001 page of 1 13 CECC 90104-xxx Date of issue ELECTRONIC COMPONENT OF ASSESSED QUAL
23、ITY IN ACCORDANCE WITH CECC 90000:Generic specification: monolithic integrated circuits, and CECC 90100:Sectional specification, digital monolithic integrated circuits FAMILY SPECIFICATION for C.MOS 4000 B and 4000 UB series (digital devices) TYPICAL CONSTRUCTION:Silicon complementary MOS, buffered
24、(B) and unbuffered (UB) outputs, cavity and non cavity packages. CAUTION:THESE ARE STATIC SENSITIVE DEVICES Outline and dimensions: In accordance with IEC Publication 191-2 See detail specification for specific type Assessment levels: R, S, T and V Terminal connections, lead plating and material: Se
25、e detail specification for specific type 1Limiting conditions of use for the family (not for inspection purposes) 1.1Maximum supply voltage, positiveVDD = + 18 V 1.2Maximum supply voltage, negativeVDD = 0,5 V 1.3Maximum positive input voltageVI = VDD + 0,5 VSee Note 1 1.4Maximum negative input volta
26、geVI = 0,5 V 1.5Maximum power dissipation per output and per package See detail specification 1.6Maximum continuous current (any input) |I| = 10 mA 1.7Maximum continuous current into any output See detail specification NOTE 1Except for transient (See 1.10 and 2.14.2) See the relevant Qualified Produ
27、cts List (QPL) for availability of components qualified to this specification Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 2 BSI 03-2000 2 Recommended conditions of use and associated char
28、acteristics for the family (not for inspection purposes) These apply over the operating temperature range, unless otherwise stated. All voltages are referenced to VSS 1.8Operating temperature range TambFull= 55 to + 125 C Limited = 40 to+ 85 C 1.9Storage temperature range Tstg 65 to + 150 C 1.10Tran
29、sient energy ratingSee detail specification SymbolVDD(V)Tamb = Tamb min. Tamb = + 25 C Tamb = Tamb max. Unit 2.1Quiescent device current VIL = 0 V, VIH = VDD 2.1.1For full operating temperature rangea Gates5 10 15 0,25 0,5 1 0,25 0,5 1 7,5 15 30 Buffers, flip-flops5 10 15 1 2 4 1 2 4 30 60 120 MSI5
30、10 15 5 10 20 5 10 20 150 300 600 LSI IDDA 5 10 15 15 25 50 15 25 50 375 750 1 500 4A2.1.2For limited operating temperature rangea Gates5 10 15 1 2 4 1 2 4 7,5 15 30 Buffers, flip-flops5 10 15 4 8 16 4 8 16 30 60 120 MSI5 10 15 20 40 80 20 40 80 150 300 600 LSI5 10 15 50 100 200 50 100 200 375 750 1
31、 500 a The Detail Specification shall specify the applicable group Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-20003 SymbolVDD(V)Tamb = Tamb min. Tamb = + 25 CTamb = Tamb max. Unit
32、 2.2Low level output voltage VIL = 0 V, VIH = VDD |I0| 1 4A VOLA5 10 15 0,05 0,05 0,05 0,05 0,05 0,05 0,05 0,05 0,05 V 2.3High level output voltage VIL = 0 V, VIH = VDD |I0| 1 4A VOHB5 10 15 4,95 9,95 14,95 4,95 9,95 14,95 4,95 9,95 14,95 V 2.4Low or high level output voltage applies for worst case
33、input conditions 2.4.1B series Low or high level output voltage at |I0| 1 4A VIL = 1,5 V for VDD =5 V VIL = 3,0 V for VDD = 10 V VIL = 4,0 V for VDD = 15 V VOLA5 10 15 0,5 1,0 1,5 0,5 1,0 1,5 0,5 1,0 1,5 V VIH = 3,5 V for VDD =5 V VIH = 7,0 V for VDD = 10 V VIH = 11,0 V for VDD = 15 V VOHB5 10 15 4,
34、5 9,0 13,5 4,5 9,0 13,5 4,5 9,0 13,5 V 2.4.2UB series Low or high level output voltage at |I0| 1 4A VIL = 1,0 V for VDD =5 V VIL = 2,0 V for VDD = 10 V VIL = 2,5 V for VDD = 15 V VOLA5 10 15 0,5 1,0 1,5 0,5 1,0 1,5 0,5 1,0 1,5 V VIH = 4,0 V for VDD =5 V VIH = 8,0 V for VDD = 10 V VIH = 12,5 V for VD
35、D = 15 V VOHB5 10 15 4,5 9,0 13,5 4,5 9,0 13,5 4,5 9,0 13,5 V Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 4 BSI 03-2000 NOTE 2Unless otherwise specified in the detail specification. NOTE
36、3For devices with symmetrical outputs the values for IOHB are equal to those for IOLB. SymbolVDD(V)Tamb = Tamb min. Tamb = + 25 CTamb = Tamb max. Unit 2.5Output low (sink) current (see Note 2) VIL = 0 V, VIH = VDD 2.5.1For full temperature range V0 = 0,4 V V0 = 0,5 V V0 = 1,5 V 5 10 15 0,64 1,6 4,2
37、0,51 1,3 3,4 0,36 0,9 2,4 mA 2.5.2For limited temperature range IOLB V0 = 0,4 V V0 = 0,5 V V0 = 1,5 V 5 10 15 0,52 1,3 3,6 0,44 1,1 3,0 0,36 0,9 2,4 2.6Output high (source) current (see Note 2 and Note 3) VIL = 0 V, VIH = VDD 2.6.1For full temperature range V0 = 4,6 V V0 = 9,5 V V0 = 13,5 V IOHB 5 1
38、0 15 0,25 0,62 1,8 0,2 0,5 1,5 0,14 0,35 1,1 mA 2.6.2For limited temperature range V0 = 4,6 V V0 = 9,5 V V0 = 13,5 V 5 10 15 0,2 0,5 1,4 0,16 0,4 1,2 0,12 0,3 1,0 2.7Input leakage current VIL = 0 V, VIH = VDD |IIA|4A 2.7.1For full temperature range 150,10,11,0 2.7.2For limited temperature range 150,
39、30,31,0 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-20005 SymbolVDD(V)Tamb = Tamb min. Tamb = + 25 C Tamb = Tamb max. Unit 2.8Three-state output leakage current VIL = 0 V, VIH = VD
40、D combined to obtain a high impedance output state |IOZA|4A 2.8.1For full temperature range150,40,412 2.8.2For limited temperature range 151,61,612 2.9Input capacitance per unit load (any input) CIA7,5pF 2.10Noise margin at low level output (equal to difference between VIL and VOL values as given in
41、 2.4) 2.10.1 B series VNLB 5 10 15 1 2 2,5 1 2 2,5 1 2 2,5 V 2.10.2 UB series5 10 15 0,5 1 1 0,5 1 1 0,5 1 1 2.11Noise margin at high level output (equal to difference between VIH and VOH values as given in 2.4) 2.11.1 B series VNHB 5 10 15 1 2 2,5 1 2 2,5 1 2 2,5 V 2.11.2 UB series5 10 15 0,5 1 1 0
42、,5 1 1 0,5 1 1 2.12Supply voltage range (to be tested at VDD = 5; 10 and 15 V) VDDB+3+3+3V VDDA+ 15+ 15+ 15 Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 6 BSI 03-2000 2.14 Supplementary in
43、formation 2.14.1 Unused inputs: Unused inputs shall be connected to the appropriate logic voltage (e.g, either VSS or VDD or associated input). 2.14.2 Transient energy protection C.MOS circuits have built-in protection circuits on all inputs to reduce the possibility of damage to the input gate oxid
44、e of the device by the transfer of electrostatic charge. Output gates may be similarly protected. A schematic may be given, for example: Generally used values: (see also relevant detail specification) RIS = 200 to 2 000 7 nom ROS = 10 to 1 000 7 nom SymbolVDD(V) Tamb = Tamb = Tamb = Tamb min. + 25 C
45、 Tamb max. Unit 2.13Propagation and transition timestPLHA tPHLA Load networks:tTLHA For normal outputs:tTHLA5 tPHZA tPZHA10See relevant detail ns tTLZAspecification tTZLA15 tPLZA For three-state outputs:tPZLA tTHZA tTZHA Licensed Copy: London South Bank University, London South Bank University, Sat
46、Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 BSI 03-20007 BVD1 = 50 to (80) to 120 V BVD2 = 20 to 50 V BVD3 = 20 to 50 V BVD4 = 20 to 50 V BVD5 = 20 to 50 V BVD6 = 50 to (80) to 120 V BVD7 = 20 to 50 V 2.14.3 Variation of parameters with temperature should be given i
47、n the format shown below; the curves given here show the general trend. Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:27:33 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90104:1981 8 BSI 03-2000 2.14.4 Variation of switching times with load capacitance
48、 shall be given in the detail specification. Due to the very low input current requirements for C.MOS, there is practically no DC output loading capability limitation when driving other C.MOS inputs. The actual fan-out of the C.MOS device is limited by a capacitance load consideration based on the d
49、esired system operating frequency. The effects of capacitive load on the dynamic characteristics shall be given. The curves shown below give the general trend of transition times versus load capacitance, which implies the general trend of propagation times versus load capacitance. Normalized to CL = 50 pF value 3 Inspection requirements All tests shall be performed at Tamb = 25 5 C unless otherwise stated. The clause numbers refer to the generic specification CECC 90000, unless otherwise s