1、附录B翻译原文ElectronicdesignautomationKeywordEDA;IC;VHDLlanguage;FPGAPROCESSDESCRIPTION.Threeobstaclesinparticularbedevilicdesignersinthisdawnofthesystemonachip.ThefirstisactuallyaShOrtfan-thehardwareandsoftwarecomponentsofthedesignlackaunifyinglanguage.Then,asthenumberoflogicgatesperchippassesthemillion
2、marks,verificationofadesig11,scorrectnessisfastbecomingmorearduousthandoingthedesignitself.Andfinally,notonlygatecountsbutchipfrequenciesalsoareclimbing,sothatgettingadesigntomeetitstimingrequirementswithouttoomanydesigniterationsisarecedinggoal.Asisthewontoftheelectronicdesignautomation(EDA)communi
3、ty,theseconcernsarebeingattackedbystart-upcompaniesledbyafewindividualswithbigideasandalittleseedmoney.PARLEZ-VOUSSUPERLOG?Asystemonachipcomprisesbothcircuitryandthesoftwarethatrunsonit.Suchadevicemaycontainanembeddedprocessorcorerunningasoftwaremodem.Mostoften,afterthechip,sfunctionalityisspelledou
4、t,usuallyonpaper,thehardwareCOm-potentishandedofftothecircuitdesignersandthesoftwareisgiventothepro-grammars,tomeetupagainatsomelaterdate.Thepartofthechipsfunctionalitythatwillendupaslogicgatesandtransistorsiswrit-teninahardwaredesignIanguage-VirologyorVHDL,whilethepartthatwillendupassoftwareismosto
5、ftendescribedintheprogramminglanguageCorC+.Theuseofthesedisparatelanguageshamperstheabilitytodescribe,model,anddebugthecircuitryoftheICandthesoftwareinacoherentfashion.Itistime,manyintheindustrybelieve,foranewdesignlanguagethatcancopewithbothhardwareandsoftwarefromtheinitialdesignspecificationrightt
6、hroughtofinalverification.JustsuchanewlanguagehasbeendevelopedbyCo-DesignAutomationInc.,SanJose,Calif.Beforelaunchingsuchanambitiousenterprise,cofoundersSimonDavidmann,whoisalsochiefoperatingofficer,andPeterFlakeruledouttheusefulnessofextendinganexistinglanguagetomeetSyStem-on-chipneeds.Amongthecand
7、idatesforextensionwereC,C+,Java,andVerilog.Adesignlanguageshouldsatisfythreerequirements,maintainedDavidmann.Itshouldunifythedesignprocess.Itshouldmakedesigningmoreefficient.Anditshouldevolveoutofanexistingmethodology.Noneoftheexistingapproachesfilledthebill.SoDavidmannandFlakesetaboutdevelopingnewc
8、o-designlanguagecalledSuperlog.AnaturalstartingpointwasablendofVirologyandCsincezzfromanalgorithmpointofview,alotofVirologyisbuiltonC,explainedDavidmann.ThentheyspicedtheblendwithbitsandpiecesofVHDLandJava.FromVirologyandVHDL,Superloghasacquiredtheabilitytodescribehardwareaspectsofthedesign,suchasse
9、quential,combinatorial,andmultivaluedlogic.FromCandJavaitinheritsdynamicprocessesandothersoftwareconstructs.Evenfunctionslikeinterfaces,protocols,andstatemachines,whichtillnowhaveoftenbeendoneonpaper,canbedescribedinthenewlanguage.Tosupportlegacycodewritteninahardwaredescriptionorprogramminglanguage
10、SuperlogallowsbothVirologyandCmodulestobeimportedanduseddirectly.Itisimportantforthelanguagetobeinthepublicdomain,accordingtoDavidmann.Thecompanyhasalreadybeguntoworkwithvariousstandardsorganizationstothisend.Nottobeoverlookedistheneedforasuiteofdesigntoolsbasedonthelanguage.RecentlyCo-Designidenti
11、fiedanumberofelectronicdesignautomationcompanies,amongthemMagmaDesignAutomation,Sente,andViewlogic,thatwilldeveloptoolsbasedonSuperlog.Co-Designwillalsodevelopproductsforthefrontendofthedesignprocess.ARACETOTHEFINISHNoteveryoneisconvincedthatanewlanguageisneeded.SystemC,amodelingplatformthatextendst
12、hecapabilitiesandadvantagesofCC+intothehardwaredomainhasbeenproposedasanalternative.SuchlargeandpowerfulcompaniesasSynopsys,Coware,LucentTechnologies,andTexasInstrumentshavebandedtogetherundertheOpenSystemCInitiativetopromotetheirversionofthenext-generationdesignplatform.TogetSystemCofftoarunningsta
13、rt,thegroupoffersamodelingplatformfordownloadofftheirWebsitefreeofcharge.Theirhopeisalsotomaketheirplatformthedefactostandard.TherationalefordevelopingSystemCwasstraightforward,accordingtoJoachimKunkel,generalmanagerandvicepresidentoftheSystemLevelDesignBusinessUnitatSynopsys.Itwastohaveastandardlan
14、guageinwhichsemiconductorvendors,IPvendors,andsystemhousescouldexchangesystem-levelIPandexecutablespecifications,andtheelectronicdesignautomationindustrycoulddevelopinteroperabletools.SupportersofSystemCbelievethatthewould-bestandardhastobebasedonC+becauseitallowscapabilitiestobeaddedtoitwithoutleav
15、ingthelanguagestandard,KunkeltoldJEEESpectrum.MostsoftwaredevelopersuseC+andmanysystemsdevelopersuseC+alreadytodescribetheirsystemsatabehaviorallevel.Buttillnowithasnotbeenpossibletodescribehardwareusingthelanguage.ThedevelopersofSystemChavesolvedthatproblembydefiningnewC+classlibrariesandasimulatio
16、nkernelthatbringtoC+allofthecapabilitiesneededtodescribehardware.zzThesenewclassesimplementnewfunctionality,explainedKunkel.Forexample,bitvectors-stringsofzerosandones-andalltheoperationsthatyouwoulddoonthem.TheSystemCdevelopersalsoprovidedaclassofsignedandunsignednumbers,thenotionofasignal,andother
17、conceptsneededtomodelhardware.Therearestillsomeholes,however.Forexample,itisstillnotpossibletosynthesizeagate-levelnetlistfromaSystcmCdescription.RutsynthesistoolsforSysteniCwouldheanaturalresultofbroadacceptanceofthelanguagewithintheusercommunity,accordingtoKunkel.ItremainstobeseenwhetherSystemCorS
18、uperlogwinsoutintheend.LeastdesirablewouldbeanoutcomeliketheimpassebetweenVirologyandVHDL,inwhichbothprevailed,forcingelectronicdesignautomationvendorstosupportbothplatformsinawastefulduplicationofeffort.THEVERIFICATIONNIGHTMAREIftoday,scomplexICsaretoughtodesign,theyareverymuchtoughertoverify.Avari
19、etyoftoolsareavailable,eachwithitsprosandcons.Emulationtranslatesadesignintofie1d-prOgrammab1egatearrays(FPGAs).Presumably,ifthearrayworksasplanned,thefinalchipwillalso.TheemulationplatformalsoenablesdesignerstotryOlllthesoftwarethatwillrunontheASIC.Theapproach,though,isslow.Typicalemulationsystemsr
20、unatafewmegahertz.Atroughlyonemillioncyclespersecond,designersarcnotgettingenoughperformanceoutoftheiremulationsystemstoverifyorunderstandsomeofthethingsthataregoingonwithvideogenerationorhighbandwidthcommunications,saidJohnGallagher,directorofmarketingforSynplicityInc.,Sunnyvale,Calif.Theymustproce
21、ssalargenumberofoperationstoensuretheirfunctionalityiscorrect,headded.Thereasonthatemulationsystemsaresoslow,accordingtoGallagher,isthattheyroutethedesignthroughmanyFPGAsandmanyboards.Simplicitysolutionistouseafewhigh-endFPGAshavingoveronemilliongatesrunningat100MHz.Typically,amillionFPGAgatestransl
22、atesinto200000ASICgates.Puttingninesuchchipsonaboardinathree-by-threearrayallowsdesignerstorepresentUpmillionASlCgates.Androutingdelaysaregreatlycurtailedbecauseeachchipisnomorethantwohopsawayfromanyotherchipinthearray.Thecompany%product,calledCertify,isnotintendedtocompetewithreconfigurableemulatio
23、nsystems,whichareveryeffectiveatdebuggingdesignsduringtheinternaldesignprocess,explainedGallagher.Rather,itisatrueprototypeofthesystem,runningatspeedsthatmayapproachtherealthing.Certifyhandlesthreefundamentaloperations,saidGallagher.Thefirstispartitioning,orbreakingsuptheASICregistertransferlevel(RT
24、L)codeintodifferentFPGAs.Itdoessynthesis,turningtheRTLcodeintoASICgatesequivalenttothefinalASICgates.Thenitdoestiminganalysis.zzWehave11,tjustlinkedtogetherthedifferenttools,“heexplained.Wehavetakaoursynthesisalgorithms,betweenthepartitioningcapabilities,andlaidthetiminganalysisacrossthat.Inaddition
25、toemulation,twocomplementaryapproachestodesignverificationaresimulationandmodelchecking,atypeofformalverification.Simulationappliesvectorstoasoftwaremodelofadesignandcheckstoseciftheoutputhasthecorrectvalue.Theapproachisstraightforward,butisbecomingincreasinglytortuousasdesignsbecomemorecomplicateda
26、ndthenumberofpossibletestvectorsmushrooms.Sorecently,electronicdesignautomationcompanieshavebeenturningtomodelcheckingtoprovethatdesignsarecorrectlydone.Thestickingpointwithmodelcheckingisitsgreatdifficultyofuse.Itisnotformostengineers,zzsaidSimonNapper,chiefoperatingofficerOFInnol-ogicSystemsInc.,S
27、anJose,Calif.Theusagemodelisverydifficult-itchecksproperties.Butthedesignerisn,tfamiliarwithwhatPpropertyis-heisusedtosimulationandstatictiming,zzAsaremedy,InnoLogicdevelopedasymbolicsimulationtool,whichblendssimulationandformalverification.ItisaVirologysimulatorexceptinsteadofsendingIsandOsthrought
28、helogic,thetoolpropagatessymbolorsymbolsplusbinaryvalues.Theusergainsimprovedfunctionalcoveragedongwithmuchfasterverification.Toillustrate,tocompletelyverifyafourbitadderwouldrequire256binaryVeCtors-andtake256simulationcycles.Withsymbols,ittakesjustonecycle.Justaswithformalverification,therearelimit
29、stothecomplexityofthecircuitsthatsymbolicsimulationcancompletelyverily.Bothhavetroublewithmultipliers,forexample.Amodelcheckerwillgrindandgrindandneverproducearesult,explainedNapper.Butinourtoolwetakesomesymbolinputsandswitchthemtobinaryvalues,thatreducesthejobfroma32-toa16bitmultiplier.Andwereportt
30、otheuserthatwewereabletoverifytheuppertheoperands,zzInnoLogichasannouncedtwoVersifiesofsymbolicsimulation.ES-XVverifiesdesignswritteninVirology.EXP-CVismeantforcustomdesignsandmemoryblocks.THETIMEISRIGHTThoughthedesignofICswithsemiconductorgeometriesbelowO.25pmfacechallengesthroughoutdevelopment,som
31、eofthebiggesthurdlesoccurduringphysicaldesign,whenthegatesareplacedonthechipandtheinterconnectsareroutedbetweenthemProblemsoccurhereforanumberofreasons.First,thecapacitance,resistance,andinductanceoftheinterconnectscannotbeignored,astheywereinolder,largertechnologies.Crosstalkbetweeninterconnects;no
32、wclosertogether,mustalsobecontrolled.Severaliterationsthroughsynthesisandplacementmaybenecessarytoachievetherequiredtiming,ifitcanbeaccomplishedatall.ThesolutionproposedbyMontereyDesignSystemsInc.,Sunnyvale,Calif.,iscalledglobaldesigntechnology.Thisproprietarycomputingapproachsimultaneouslyexplores,
33、analyzes,andoptimizesallaspectsofthephysicaldesign.ThetintproductcontainingthetechnologyisDolphin,whichwasannouncedinApriloflastyear.Dolphinsimultaneouslyplacesandroutereachgateandflip-flopusingtheresultsortheanalysisandmaintainingallspecifiedconstraints.(Mostplace-and-routetoolssequentiallyanalyzet
34、helayoutforeachtypeofconstraint.)Itperformstimingandlogicoptimizationforeveryplacementmove.TimingclosureistoppriorityfordevelopersoftheBlastFusionphysicaldesignsystemfromMagmaDesignAutomations.,Cupertino,Calif.Itsmethodology,calledFixedTiming,bringstimingwithinspecifiedlimitswithoutiteratingbetweens
35、ynthesisandphysicaldesign.Basically,heapproachfixestimingfirst,thenadjustscellsizestoachievethetimingrequirements.Varyingthecellsizesalwayshetooltosupplytherightdrivestrengthortheload.EDAONTHEWEBAsestablishedelectronicdesignautomationcompaniestrytosortouthowtoutilizetheinternetintheirproductInks,sma
36、ller,moreagilecompaniesandStart-upsarccoiningupwithinnovativeproductsandservices,mainlyintheareasordesignmanagement.ApioneerinthisareaisSynchronicityInc.,avirtualcompanyheadquarteredinMarlboro,Mass.Synchronicityisnowbeingjoinedbyothercompaniesseekingtousetheinternettoadvantage.TheconcernofCCAES.COM,
37、Milpitas,CalifaproviderofWeb-basedengineeringtoolsfor;designautomation,istheextractionofusefulinformationaboutICs,chipsets,andboardsfromsuppliers5Websites.Theissue,accordingtoMichaelBitzko,presidentofthecompany,isthatdesignersofproductsbasedontherecomponentsneedtobeabletoobtaininformationaboutthemqu
38、icklyandrouteittotheirengineering,manufacturing,andprocurementdepartmentsasquicklyaspossible.Inanutshell,z,saidBitzko,“peopleusedtotakeweekstogetdatasheets.ThenalongcanetheWebandPDF-formatteddocuments.Butinordertocreate,ray,schematicsymbolsandfootprintsfurprintedcircuitboards,informationfromPDFdocum
39、entsmustoftenbereentered-acostlyandtime-consumingprocesswhentimetoinfarctisaconcern.CCAES.COM,sproductsarebasedontheelectroniccomponentinterchange(ECIX)standarddevelopedbyEDAstandardsorganizationSI,Austin,Texas,andontheExtensibleMarkupLanguage(XML),thatallowsthecreationorWeb-baskdocumentshaving(more
40、functionalitythanwiththeconventionalHypertextMarkupLanguage(HTMl.).ThecompanysproductsincludeQuickDataServer,aparametricsearchengineforelectroniccomponentinformation,andQuickdataMiner,whichtransforminformationcontainedinPDFdatasheetsintoausableform.ThemissionorGenedaxInc.,Portland,Ore.istousetheWebt
41、oincreasedesignedabilitytocreateandmanagelarge,complexdesigns,toirondesignICLISC,andtoimproveaccesstointellectualproperty.Thecompanyplanstoannounceaproductinthefirstquarterortheyear.JohnOtt,vicepresidentofsalesandmarketing,toldSprctmnithatitsproductswillbebasedontheoperatingsystemsandbrowsersdevelop
42、edbyMicrosottCorp.,Redmond,Wash.Also,thecompanysupportsacollaborativeWebsite,www.fatchip,comthatshowswhatthetechnologycando.ThesiteincludesasearchenginebasedonAltaVistatechnologythatsearchestheWebsitesofcompaniesrelatedtodesignautoillation.Ottelaborated,WealsohaveafreeInternetlocatorserverthatletspe
43、opleuseNetmeetingaMicrosoftproductforremotesharingofcomputerdesktopsandaWebboardwhereyoucanpostquestionsandgetanswers,zzOtheraspectsofelectronicdesignontheWebshavebeenslowerintakingoffthandesignandinformationmanagement.ButTransimCorpalsobaredinPortland,Ore,hastakenabigsteptowardWeb-baseddesigntools.
44、Itsproduct,Websim,isaninterfacebetweenaWebbrowserandSimples,thecompany,spower-supplysimulator.Websimallowsdesigners,usingSimplis,tosimulatedesignsovertheInternet.Soratherthanporingoverdatasheetsandlookingatrangesofvalues,designerscanseeactualwaveforms,explainedNclsGahbert,Transimpresidentandchiefexe
45、cutiveofficer.TransimisworkingwithsupplierstosetupcomponentmodelssothatdesignerscanlogontothesuppliesWebrite,selectpartsfortheirpowersupply,entersetuportestconditions,andrunthesimulationonline.UsersneednothingmorethanaWebbrowser.ThesimulationisrunonTransim,sranchofsixstriversfromSunMicrosystems.Thec
46、ompanyhasteamedupwithNationalSemiconductorCorp,SantaClara,Calif.,toprovidethisserviceforNationaTscustomers.Thecostisonaper-usebasisandisaminimalUS$10.附录C翻译中文电子设计自动化关键字电子设计自动化；集成电路；VHDL语言；现场可编程门阵列在这个片上系统开始出现的时候，有三个问题一直困扰着集成电路设计者。首先就是缺乏一些东西即设计的硬件部件与软件部件之间缺少统一的语言。这样由于每一个芯片的逻辑闸门的数量超过了百万，因此，对设计正确性的验证瞬间比设
47、计本身更加艰巨。另外，不仅仅是闸门数量问题，集成芯片的频率也在加大。因此，为了满足时间需要，做出一个不用反复设计的设计是遥远的目标。由于已长期研究电子设计自动化，对于这方面的关注经常受到一些新建的公司抨击。那些公司是由几个志向远大启动资金缺乏的人领导。您说superlog?芯片系统由电路和软件组成运行。这样的系统一般包含一个嵌入的处理器核运行软件调制解调器。通常，芯片的功能被写在纸上后，硬件部件就交给了集成电路设计者，软件部件就给了程序设计者，在以后的某个闸门在合起来组在一起。芯片的一局部功能在逻辑闸门核晶体管被写入硬件描述语言-verilog语言或VHDL语言时结束。而另外一局部功能将在软件
48、被描述在编程语言C或C+中结束。这种不同语言的使用给描述，仿制，调试集成电路的线路和软件的条理清晰方面都带来了很大的不便。从工业角度上看我们相信是时候推出一种新的设计语言处理硬件和软件的问题,使系统从最初的设计规格直达最后的检验。加利福尼亚州的协同设计自动化公司的Sarljose开展了这种新型语言。在成立这个蒸蒸日上的企业前，合作者，现经营主任simondavidmann和peterflake已经得出了为满足片上系统开展现有语言的实用性。选为被开展的现有语言有C,C+,Java和Verilogodavidmann说一种设计语言必须满足三个需求。第一应该连接设计过程。第二应该使设计更为高效。第三
49、应该由一种现存的方法演变而来。没有一种现存的方法满足这些需求，于是davidmann和flake决定创造一种新的协同设计语言，并命名为superlogodavidmann解释说“一个很自然的基准点就是连接verilog语言和C语言，从算法观点上来看,大多数verilog语言都是建立在C语言基础上的。这时用比特和VHDL语言与Java语言将其连接起来。从VeriIOgandVHDL方面，SUPerIOg获得了设计中描述硬件方面的能力，例如顺序逻辑，组合逻辑和多值逻辑。从C和Java方面superlog又集成了动态处理器和其他软件编制。甚至像接口程序，活动网络路由协议和状态机等现阶段仍常被写在纸上的功能也能被新的语言描述了。为了处理已经存在的硬件描述或编程语言的遗留问题，superlog允许verilog语言和C语言模块输入并允许其直接使用。davidmann说这门语言推广到公共领域使用是非常重要的。公司已经开始和不同标准的组织合作工作到达其推广的目的。不被无视是建立在语言上的设计工具套
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